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2016-06-02PSCI: remove arisc from PSCI_SHUTDOWNAndre Przywara
The arisc can tell the PMIC to power down the SoC, but we are going to loose the arisc, so replace the arisc implementation for shutdown with a warning and a hang until we have the PMIC code in place. Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2016-06-02PSCI: replace arisc call for PSCI_RESET with watchdog resetAndre Przywara
We cannot ask the arisc for help anymore, so let's program the watchdog to trigger a reset in the shortest possible time period to achieve a system reset if non-secure world requests it. Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2016-06-02PSCI: rework sun50i CPU state management to avoid the ariscAndre Przywara
Rework the SMP secondary cores bringup and shutdown to not use the arisc blob. Instead let ATF do its job and enable/disable the power clamp and further registers. Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2016-06-02sun50i: add OpenRISC stop code near BL31 start pointAndre Przywara
As ATF is now disguised as the SCP, eventually boot0 will power on the arisc and it will try to let it execute OpenRISC code. Provide some OpenRISC code to shut the core down again, by setting the shutdown bit in the PMR special register. The code sequence is: l.xor r0, r0, r0 ; clear r0 l.ori r1, r0, 0xc0 ; r1 = 0xc0 l.mtspr r0, r1, 0x4000 ; PMR(@0x4000) := r1 (0x40) Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2016-06-02bl31: remove no longer needed boot0 headerAndre Przywara
As ATF now lives in SRAM, we can't load it directly as the ATF binary anymore (it would always be loaded into DRAM then). Instead we disguise it as the SCP, which does not require a specific boot0 header. Remove all the code that was prefixing the binary with the boot0 header (which was a bit misplaced in generic code anyway). Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2016-06-02sun50i: enter U-Boot in AArch64Andre Przywara
Drop back into non-secure world into the AArch64 state now. This allows U-Boot to run in 64-bit mode, so no need to call back into the firmware to eventually launch 64-bit kernels. Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2016-06-02sun50i: remove now unused trusted mappingAndre Przywara
Without the arisc there is no need to reserve a memory mapping for later. Remove the entries from the data structure to avoid unneeded mappings. Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2016-06-02sun50i: move ATF into SRAM A2Andre Przywara
On some boards there are issues with SRAM C, so we move ATF to run from SRAM A2 for now. It actually gives us > 32KB of working space, so a debug version works here as well. SRAM A2 is documented to be secure only, which seems like a good fit for secure monitor runtime code. But apparently this is not really true, since it's still accessible for the non-secure side. Also SRAM A2 is tighly coupled to the arisc (OpenRISC controller) and thus not the ideal place to be hogged with ARM code. Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2016-06-02sun50i: move ATF into SRAM CAndre Przywara
This moves ATF from the (unsecured) DRAM into SRAM C. Not fully decided if this is the place it should eventually live, but it's better than using the beginning of DRAM for it. SRAM C could be programmed to be secure only (not done here yet). Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2016-06-02sun50i: mmap: dont map the whole device area, exclude SRAMAndre Przywara
If we soon run in SRAM, the memory mapping code maps .text & friends anyway, so we can confine the device mapping to the actual memory region used by devices. We exclude the SRAM/BROM regions. Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2016-06-02sun50i: limit ATF sizeAndre Przywara
Without the arisc we don't need any buffer memory for SCP communication anymore, so we can drastically reduce the memory footprint of ATF from 2MB to 64KB. This is needed to put ATF eventually in SRAM. Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2016-06-02sun50i: fix comment about NS_IMAGE_OFFSET locationAndre Przywara
U-Boot gets loaded at 160MB into the DRAM, not at 128MB. Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2016-06-02linking: fix LENGTH attribute in linker scriptAndre Przywara
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2016-06-02sun50i: smc calls: remove (in)secure register read/write service callsAndre Przywara
There are two SMC calls that allowed non-secure software to read and write _every_ "register", in fact memory locations. This breaks the whole secure/non-secure separation scheme and thus has to go. Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2016-06-02assert: revert removal of assertion debug printAndre Przywara
Allwinner removed the code which prints a meaningful debug output if an assertion triggered. Revert that part to give a clue about what's wrong instead of just silently halting. Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2016-06-02sun50i: remove unneeded platform-specific GIC setupAndre Przywara
The Allwinner code defined a platform specific GIC setup. However we don't need secure IRQs or a special setup, so we can easily go with the default ARM GIC setup provided by the driver. Remove the unneeded code file, associated calls and code lines. Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2016-06-02drivers: arm_gic: remove GICv3 assertionAndre Przywara
The generic ARM GIC setup code has an assertion about a valid GICv3 redistributor base address. Remove this to allow to setup GICv2s using the generic interface. Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2016-06-02drivers: arm_gic: allow zero secure interruptsAndre Przywara
Currently the generic GIC driver code has an assert to halt if no valid pointer to the list of secure interrupts is specified. Rework this to barf only if the number of secure interrupts is greater than zero. This allows to specify zero secure interrupts and pass a NULL pointer for the table address. Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2016-06-02sun50i: platform.mk: rewrap source file listingAndre Przywara
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2016-06-02sun50i: introduce get_highest_el() functionalityAndre Przywara
Add a function to get the highest implemented exception level and use that for entering BL3-3 in. Also we make the bit-size we enter non-secure world a parameter, so that we can easily switch between AArch32 and AArch64. (HACK: Keep entering U-Boot still in AArch32 SVC for now.) Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2016-06-02sun50i: remove unneeded platform specific address definitionsAndre Przywara
sun50iw1p1.h contains a lot of register addresses and platform specific defines, the vast majority of them both unused by the code and also not needed for a bl31 setup. Remove the header file and pull the actually needed definitions into sunxi_def.h. Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2016-06-02sun50i: clean up serial (debug) driverAndre Przywara
The serial debug driver is hard to read. Also it uses a C struct to describe a fixed hardware device' register layout. Clean up the code to be more readable and switch to the usual (BASE_ADDR + REG_OFFSET) scheme for accessing registers. Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2016-06-02sun50i: remove unneeded sunxi_config_setup()Andre Przywara
This function does nothing, apparently it was copied from the FVP code. Remove its definition and the call. Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2016-06-02sun50i: define empty print_plat_interconnect_regsAndre Przywara
Instead of commenting the routine from FVP and the call, simply define the print_plat_interconnect_regs macros as empty, which is the recommended way in case there is no interconnect information available. Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2016-06-02sun50i: remove Allwinner hash outputAndre Przywara
We actually have the short SHA1 of the HEAD commit already in the output, so there is no need for that extra bloated code to insert it into the binary. Remove it. Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2016-06-02sun50i: MMU setup: remove unneeded EL1 versionAndre Przywara
We have macros to generate define and populate the memory map structures, but in fact need only one instance for EL3, as sunxi does not need EL1 page tables. Remove the unneeded code. Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2016-06-02sun50i: remove unneeded TSP implementationAndre Przywara
The TSP is just for testing a secure payload, which we don't need, so just remove the code. Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2016-06-02sun50i: remove unneeded BL1 and BL2 codeAndre Przywara
The sun50i port only uses BL31, so there is no need for then BL1 and BL2 code files (copied from the FVP port). Remove them. Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2016-06-02sun50i: remove unneeded AEM and A57 codeAndre Przywara
No need to compile those code in. Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2016-06-02sun50i: clean up sunxi_security codeAndre Przywara
Remove dead code, unused definitions and stream-line the code. Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2016-06-02sun50i: simplify topology setupAndre Przywara
The topology code was apparently copied from the ARM FVP model, which is very versatile and allows for a sophisticated, configurable topology setup. Allwinner SoC on the other hand are at best multi-cluster - the A64 in fact has only one cluster. Simplify the sunxi specific topology code to support two affinity levels at most - this drastically reduces the code size and makes it much more readable. Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2016-02-16sun50i: remove unused sunxi_gic_initAndre Przywara
2016-02-16sun50i: remove unused CCI initAndre Przywara
2016-02-16sun50i: fix timer frequencyAndre Przywara
The architected timer is hardwired to be driven by the 24 MHz clock. Remove all code that tries to determine this dynamically. Also fix the actual number, which is not 24 * 2^20, but 24 * 10^6 Hz. Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2016-02-16sun50i: platform.S: clean up serial consoleAndre Przywara
Add some constants to the console code to make it more readable.
2016-02-06sun50i: plat_helpers.S cleanupAndre Przywara
A lot of code is not needed: - no need for empty function which have a default implementation - no need for A57 code and Juno workarounds - no need for specific core enumeration in a single cluster SoC
2016-02-04enter non-secure world in non-secure EL2Andre Przywara
2016-02-04sun50i: bl33_entry: reactivate code (but still use SVC32)Andre Przywara
2016-02-04Makefile: remove copying of final binaryAndre Przywara
After the actual build process the Makefile copied the resulting binary into Allwinner's build tree (for deployment). Remove this copy to allow build outside of Allwinner's build environment.
2016-02-04arisc: make debug macros -pedantic compatibleAndre Przywara
Allwinner removed "-pedantic" from the list of CFLAGS to get away with some conditional debug macros using a GNU extension. Fix those macros to use a standard compliant syntax and re-enable -pedantic.
2016-02-04Makefile: fix w/s errorAndre Przywara
2016-02-04Makefile: comment Cortex-A53 linker fix optionAndre Przywara
Newer versions of binutils' ld recognize a errata fix option to avoid issues with a certain ARM Cortex-A53 errata. Since this option is widely available yet, comment it for now to allow build with older toolchains.
2016-02-04Makefile: revert Allwinner changes to default targetAndre Przywara
Apparently for convenience reasons the Makefile was changed by Allwinner to: * build the sun50iw1p1 target by default * hardcode the cross compiler from Allwinner's toolchain * enable debug build by default Revert those changes to bring the build system back into a sane state.
2016-02-04Merge in files from Allwinners lichee BSP tarballAndre Przywara
The Pine64 Wiki[1] links to a BSP tarball, among other things containing a dump of an ARM Trusted Firmware source tree with Allwinner changes on top. Since the tarball does not contain any version history information about the changes, this commit is just the diff between the ATF 1.0 release and the files from the Allwinner provided tarball. The executable flag from many source has been removed. [1] http://wiki.pine64.org/index.php/Pine_A64_Software_Release#Linux_BSP_Related
2014-08-28Merge pull request #205 from danh-arm/dh/1.0-docsdanh-arm
Documentation for version 1.0
2014-08-28Merge pull request #204 from danh-arm/dh/user-guide-fixesdanh-arm
Fix minor issues in user guide
2014-08-28Documentation for version 1.0Dan Handley
Final updates to readme.md and change-log.md for ARM Trusted Firmware version 1.0. Also increment the version in the Makefile. Change-Id: I00fe1016c8b936834bbf7bbba7aab07f51261bbb
2014-08-28Fix minor issues in user guideDan Handley
* Fix broken link to SCP download. * Remove requirement to install `ia32-libs`. This package is no longer available in current versions of Ubuntu and is no longer required when using the Linaro toolchain. Change-Id: I9823d535a1d69136685754b7707b73e1eef0978d
2014-08-27Merge pull request #203 from danh-arm/dh/misc-docs-1.0danh-arm
Miscellaneous documentation fixes
2014-08-27Miscellaneous documentation fixesSandrine Bailleux
This patch gathers miscellaneous minor fixes to the documentation, and comments in the source code. Change-Id: I631e3dda5abafa2d90f464edaee069a1e58b751b Co-Authored-By: Soby Mathew <soby.mathew@arm.com> Co-Authored-By: Dan Handley <dan.handley@arm.com>
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