diff options
| author | Andre Przywara <andre.przywara@arm.com> | 2016-02-15 01:47:49 +0000 |
|---|---|---|
| committer | Andre Przywara <andre.przywara@arm.com> | 2016-02-16 01:36:11 +0000 |
| commit | e1dcfe6c2e940b5ba09bf2b328ea3c69d8fb0305 (patch) | |
| tree | ef2c987c5b9c06609d5a61f3a2ca56a7256cf7db | |
| parent | 77e8eee85765d55768017f653adf8132d75e5143 (diff) | |
sun50i: fix timer frequency
The architected timer is hardwired to be driven by the 24 MHz clock.
Remove all code that tries to determine this dynamically.
Also fix the actual number, which is not 24 * 2^20, but 24 * 10^6 Hz.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
| -rw-r--r-- | plat/sun50iw1p1/aarch64/sunxi_common.c | 11 |
1 files changed, 1 insertions, 10 deletions
diff --git a/plat/sun50iw1p1/aarch64/sunxi_common.c b/plat/sun50iw1p1/aarch64/sunxi_common.c index b55b3a6..665725c 100644 --- a/plat/sun50iw1p1/aarch64/sunxi_common.c +++ b/plat/sun50iw1p1/aarch64/sunxi_common.c @@ -166,16 +166,7 @@ unsigned long plat_get_ns_image_entrypoint(void) uint64_t plat_get_syscnt_freq(void) { - uint64_t counter_base_frequency; - - /* Read the frequency from Frequency modes table */ - counter_base_frequency = 24<<20;//mmio_read_32(SYS_CNTCTL_BASE + CNTFID_OFF); - - /* The first entry of the frequency modes table must not be 0 */ - if (counter_base_frequency == 0) - panic(); - - return counter_base_frequency; + return 24 * 1000 * 1000; } void sunxi_cci_init(void) |