diff options
| author | Andre Przywara <andre.przywara@arm.com> | 2016-05-02 00:50:00 +0100 |
|---|---|---|
| committer | Andre Przywara <andre.przywara@arm.com> | 2016-06-02 01:29:47 +0100 |
| commit | 633933c3d56932e6ddb54bcc2ac904f3fec206d3 (patch) | |
| tree | a2ac37e8a5308b69ab3fbf277db0347988eabf48 | |
| parent | b0ff32bc4142aecfb71234c602e9bd4b1c020ebb (diff) | |
sun50i: add OpenRISC stop code near BL31 start point
As ATF is now disguised as the SCP, eventually boot0 will power on
the arisc and it will try to let it execute OpenRISC code.
Provide some OpenRISC code to shut the core down again, by setting
the shutdown bit in the PMR special register.
The code sequence is:
l.xor r0, r0, r0 ; clear r0
l.ori r1, r0, 0xc0 ; r1 = 0xc0
l.mtspr r0, r1, 0x4000 ; PMR(@0x4000) := r1 (0x40)
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
| -rw-r--r-- | bl31/aarch64/bl31_entrypoint.S | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/bl31/aarch64/bl31_entrypoint.S b/bl31/aarch64/bl31_entrypoint.S index 6f5a7c0..8e10d6a 100644 --- a/bl31/aarch64/bl31_entrypoint.S +++ b/bl31/aarch64/bl31_entrypoint.S @@ -41,12 +41,21 @@ * ----------------------------------------------------- */ func bl31_entrypoint + b code_start + nop /* align to 8 bytes */ + .byte 0x05, 0x00, 0x00, 0xe0, 0x00, 0x04, 0x02, 0xa8 + /* l.xor r0, r0, r0 l.ori r1, r0, 0xc0 */ + .byte 0x00, 0x80, 0x00, 0xc1, 0x00, 0x00, 0x00, 0x15 + /* l.mtspr r0, r1, 0x4000 l.nop */ + /* --------------------------------------------------------------- * Preceding bootloader has populated x0 with a pointer to a * 'bl31_params' structure & x1 with a pointer to platform * specific structure * --------------------------------------------------------------- */ + +code_start: #if !RESET_TO_BL31 /* *AA32 warmreset to AA64, the high 32bit in reg R0,R1 is unpredictable |