diff options
| author | Andre Przywara <andre.przywara@arm.com> | 2016-02-15 02:03:45 +0000 |
|---|---|---|
| committer | Andre Przywara <andre.przywara@arm.com> | 2016-02-16 01:36:11 +0000 |
| commit | fc1e255c846bc0a0c72c8e6f822e64e24704e136 (patch) | |
| tree | d1e8ee383154be2497e0a7cea3b61df5c1e2f56b | |
| parent | 14cf9bf41bba096d8eef7adefaaab491c0397aa8 (diff) | |
sun50i: remove unused sunxi_gic_init
| -rw-r--r-- | plat/sun50iw1p1/aarch64/sunxi_common.c | 6 | ||||
| -rw-r--r-- | plat/sun50iw1p1/bl31_sunxi_setup.c | 26 | ||||
| -rw-r--r-- | plat/sun50iw1p1/sunxi_private.h | 2 | ||||
| -rw-r--r-- | plat/sun50iw1p1/tsp/tsp_sunxi_setup.c | 2 |
4 files changed, 2 insertions, 34 deletions
diff --git a/plat/sun50iw1p1/aarch64/sunxi_common.c b/plat/sun50iw1p1/aarch64/sunxi_common.c index ca796a1..edf2711 100644 --- a/plat/sun50iw1p1/aarch64/sunxi_common.c +++ b/plat/sun50iw1p1/aarch64/sunxi_common.c @@ -169,12 +169,6 @@ uint64_t plat_get_syscnt_freq(void) return 24 * 1000 * 1000; } -void sunxi_gic_init(void) -{ - gic_setup(); -} - - /******************************************************************************* * Gets SPSR for BL32 entry ******************************************************************************/ diff --git a/plat/sun50iw1p1/bl31_sunxi_setup.c b/plat/sun50iw1p1/bl31_sunxi_setup.c index 4237a25..dbabcf4 100644 --- a/plat/sun50iw1p1/bl31_sunxi_setup.c +++ b/plat/sun50iw1p1/bl31_sunxi_setup.c @@ -221,31 +221,7 @@ void bl31_platform_setup(void) //unsigned int reg_val; /* Initialize the gic cpu and distributor interfaces */ - sunxi_gic_init(); -#if 0 - - /* - * TODO: Configure the CLCD before handing control to - * linux. Need to see if a separate driver is needed - * instead. - */ - mmio_write_32(VE_SYSREGS_BASE + V2M_SYS_CFGDATA, 0); - mmio_write_32(VE_SYSREGS_BASE + V2M_SYS_CFGCTRL, - (1ull << 31) | (1 << 30) | (7 << 20) | (0 << 16)); - - /* Enable and initialize the System level generic timer */ - mmio_write_32(SYS_CNTCTL_BASE + CNTCR_OFF, CNTCR_FCREQ(0) | CNTCR_EN); - - /* Allow access to the System counter timer module */ - reg_val = (1 << CNTACR_RPCT_SHIFT) | (1 << CNTACR_RVCT_SHIFT); - reg_val |= (1 << CNTACR_RFRQ_SHIFT) | (1 << CNTACR_RVOFF_SHIFT); - reg_val |= (1 << CNTACR_RWVT_SHIFT) | (1 << CNTACR_RWPT_SHIFT); - mmio_write_32(SYS_TIMCTL_BASE + CNTACR_BASE(0), reg_val); - mmio_write_32(SYS_TIMCTL_BASE + CNTACR_BASE(1), reg_val); - - reg_val = (1 << CNTNSAR_NS_SHIFT(0)) | (1 << CNTNSAR_NS_SHIFT(1)); - mmio_write_32(SYS_TIMCTL_BASE + CNTNSAR, reg_val); -#endif + gic_setup(); /* Intialize the power controller */ //sunxi_pwrc_setup(); diff --git a/plat/sun50iw1p1/sunxi_private.h b/plat/sun50iw1p1/sunxi_private.h index 528f1a7..31e479e 100644 --- a/plat/sun50iw1p1/sunxi_private.h +++ b/plat/sun50iw1p1/sunxi_private.h @@ -83,8 +83,6 @@ void sunxi_configure_mmu_el3(unsigned long total_base, unsigned long); int sunxi_config_setup(void); -void sunxi_gic_init(void); - /* Declarations for sunxi_topology.c */ int sunxi_setup_topology(void); diff --git a/plat/sun50iw1p1/tsp/tsp_sunxi_setup.c b/plat/sun50iw1p1/tsp/tsp_sunxi_setup.c index 82c74af..a251b79 100644 --- a/plat/sun50iw1p1/tsp/tsp_sunxi_setup.c +++ b/plat/sun50iw1p1/tsp/tsp_sunxi_setup.c @@ -83,7 +83,7 @@ void tsp_early_platform_setup(void) ******************************************************************************/ void tsp_platform_setup(void) { - sunxi_gic_init(); + gic_setup(); } /******************************************************************************* |