diff options
author | Andre Przywara <andre.przywara@arm.com> | 2016-02-23 12:38:27 +0000 |
---|---|---|
committer | Andre Przywara <andre.przywara@arm.com> | 2016-06-02 01:27:06 +0100 |
commit | 4ee05598f9301e06f10111503fd1c7776c3741a7 (patch) | |
tree | 0c69054d1ce4bc9b80442531d44d666a0d0e8aaf | |
parent | 2148dcb390b5c20112ef16478902ea0a51b85fcd (diff) |
sun50i: MMU setup: remove unneeded EL1 version
We have macros to generate define and populate the memory map
structures, but in fact need only one instance for EL3, as sunxi
does not need EL1 page tables.
Remove the unneeded code.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
-rw-r--r-- | plat/sun50iw1p1/aarch64/sunxi_common.c | 66 | ||||
-rw-r--r-- | plat/sun50iw1p1/bl31_sunxi_setup.c | 14 |
2 files changed, 9 insertions, 71 deletions
diff --git a/plat/sun50iw1p1/aarch64/sunxi_common.c b/plat/sun50iw1p1/aarch64/sunxi_common.c index e830aef..e55ee30 100644 --- a/plat/sun50iw1p1/aarch64/sunxi_common.c +++ b/plat/sun50iw1p1/aarch64/sunxi_common.c @@ -66,42 +66,9 @@ const mmap_region_t sunxi_mmap[] = { {0} }; - - - -/******************************************************************************* - * Macro generating the code for the function setting up the pagetables as per - * the platform memory map & initialize the mmu, for the given exception level - ******************************************************************************/ -#define DEFINE_CONFIGURE_MMU_EL(_el) \ - void sunxi_configure_mmu_el##_el(unsigned long total_base, \ - unsigned long total_size, \ - unsigned long ro_start, \ - unsigned long ro_limit, \ - unsigned long coh_start, \ - unsigned long coh_limit) \ - { \ - mmap_add_region(total_base, total_base, \ - total_size, \ - MT_MEMORY | MT_RW | MT_SECURE); \ - mmap_add_region(ro_start, ro_start, \ - ro_limit - ro_start, \ - MT_MEMORY | MT_RO | MT_SECURE); \ - mmap_add_region(coh_start, coh_start, \ - coh_limit - coh_start, \ - MT_DEVICE | MT_RW | MT_SECURE); \ - mmap_add(sunxi_mmap); \ - init_xlat_tables(); \ - \ - enable_mmu_el##_el(0); \ - } - -void sunxi_configure_mmu_el3(unsigned long total_base, - unsigned long total_size, - unsigned long ro_start, - unsigned long ro_limit, - unsigned long coh_start, - unsigned long coh_limit) +void sunxi_configure_mmu_el3(unsigned long total_base, unsigned long total_size, + unsigned long ro_start, unsigned long ro_limit, + unsigned long coh_start, unsigned long coh_limit) { mmap_add_region(total_base, total_base, total_size, @@ -118,33 +85,6 @@ void sunxi_configure_mmu_el3(unsigned long total_base, enable_mmu_el3(0); } -void sunxi_configure_mmu_el1(unsigned long total_base, - unsigned long total_size, - unsigned long ro_start, - unsigned long ro_limit, - unsigned long coh_start, - unsigned long coh_limit) -{ - mmap_add_region(total_base, total_base, - total_size, - MT_MEMORY | MT_RW | MT_SECURE); - mmap_add_region(ro_start, ro_start, - ro_limit - ro_start, - MT_MEMORY | MT_RO | MT_SECURE); - mmap_add_region(coh_start, coh_start, - coh_limit - coh_start, - MT_DEVICE | MT_RW | MT_SECURE); - mmap_add(sunxi_mmap); - init_xlat_tables(); - - enable_mmu_el1(0); -} - - -/* Define EL1 and EL3 variants of the function initialising the MMU */ -//DEFINE_CONFIGURE_MMU_EL(1) -//DEFINE_CONFIGURE_MMU_EL(3) - /******************************************************************************* * A single boot loader stack is expected to work on both the Foundation FVP * models and the two flavours of the Base FVP models (AEMv8 & Cortex). The diff --git a/plat/sun50iw1p1/bl31_sunxi_setup.c b/plat/sun50iw1p1/bl31_sunxi_setup.c index 07197ad..de428ad 100644 --- a/plat/sun50iw1p1/bl31_sunxi_setup.c +++ b/plat/sun50iw1p1/bl31_sunxi_setup.c @@ -216,13 +216,11 @@ void bl31_plat_arch_setup(void) { //set smp bit before cache enable platform_smp_init(); -#if 1 - sunxi_configure_mmu_el3(BL31_RO_BASE, - (BL31_COHERENT_RAM_LIMIT - BL31_RO_BASE), - BL31_RO_BASE, - BL31_RO_LIMIT, - BL31_COHERENT_RAM_BASE, - BL31_COHERENT_RAM_LIMIT); -#endif + sunxi_configure_mmu_el3(BL31_RO_BASE, + (BL31_COHERENT_RAM_LIMIT - BL31_RO_BASE), + BL31_RO_BASE, + BL31_RO_LIMIT, + BL31_COHERENT_RAM_BASE, + BL31_COHERENT_RAM_LIMIT); } |