AgeCommit message (Collapse)Author
2017-03-08sun50iw1p1: Add ARISC emulator service.HEADlynx-3.10-without-ariscChristoph Muellner
The Allwinner BSP kernel (and the derived kernel trees from the Sunxi community) depend on some functionality provided by ATF and the ARISC firmware. In fact Allwinners ATF does not provide that functionality directly, but forwards requests to the ARISC firmware. This patch adds an emulation service, which brings the necessary functionality to the ATF (i.e. no ARISC firmware needed). The functionality includes: * DVFS (tested for frequencies in the range of 480-1152 MHz). * Access to AXP registers. * Safe returns for other required SMCs. This patch has been tested with a Linux 3.10 sunxi kernel. Signed-off-by: Christoph Muellner <>
2017-03-08sun50iw1p1: Rewrite PMIC driver.Christoph Muellner
The existing API to interact with the PMIC (AXP803) offers low-level calls to read and write PMIC registers. This patch adds two high-level APIs: * regulator-level API * task-level API The regulator-level API allows to enable, disable, and set the voltage level of regulators. The regulators are named by IDs in the form of AXP803_<regulator> (e.g. AXP803_DCDC2). The task-level API allows to perform a batch of regulator-level calls. Using this API allows to keep many invokations of the regulator-level API compact. Signed-off-by: Christoph Muellner <>
2017-03-08sun50iw1p1: Make RSB read/write calls MP-safe.Christoph Muellner
When calling rsb_read() or rsb_write() from different processors at the same time we most likely mess up with the RSB block. This patch adds a spinlock, which guarantees atomic access to the RSB block. Signed-off-by: Christoph Muellner <>
2017-03-08sun50iw1p1: Separate RSB driver from PMIC code.Christoph Muellner
This patch refactors the PMIC code and moves the RSB related code into its own module. This allows other code to access RSB devices as well and make the code more readable. Signed-off-by: Christoph Muellner <>
2017-03-08sun50iw1p1: Add function to get current CPU speed.Christoph Muellner
The function assumes that PLL CPUX is active and reads out the factors from the PLL CPUX control register. Signed-off-by: Christoph Muellner <>
2017-03-08sun50iw1p1: Generalize CPU PLL setup code for arbitrary frequencies.Christoph Muellner
Instead of having hard coded values for the CPU PLL control register, we calculate the PLL factors with the following rules: * M is always 1 (granularity is 24 MHz) * K is keept as low as possible Signed-off-by: Christoph Muellner <>
2017-02-02sun50iw1p1: Adjust PMIC setting for the A64-uQ7 (DDR3L and GbE PHY)Philipp Tomsich
For the A64-uQ7 we should set up DCDC5 (DDR) to 1.36V and DCDC4 to 1.2V (for the Micrel GbE PHY). Note that a higher DCDC5 setting (i.e. 1.5V) will also work safely, but we expect a power-saving under high system load from using the lower DDR3L voltage supported by our RAM. Per my discussion with Andre, board-specific power initialisation should eventually be conditionalised on the FDT, as seen by the ATF. However, this will require the ATF to be rebased to a more current ATF source bae first. X-AffectedPlatforms: A64-uQ7 Signed-off-by: Philipp Tomsich <>
2017-02-02sun50iw1p1: Adjust clock initialisation to follow Allwinner's guidancePhilipp Tomsich
Initialisation of clocks on Allwinner's CPUs has always been a bit tricky and should follow the following guidance: 1. Bus clock dividers should be adjusted first to keep the bus clocks within their operating limits for both the new frequency _before_ changing the PLL (compare to section in the A64 User's Guide v1.0). 2. PLLs should first be setup (with the enable-bit cleared), then be enabled and finally polled for the stable-bit to indicate the a PLL lock (compare how boot0 and Allwinner's linux releases have been changing PLLs for the A31 and subsequent chips). 3. Additionally Allwinner always injects extra delays after the PLL lock has triggered and after the clock source is changed. Without these changes, the A64 will not reliably come up beyond the clock initialisation w/ the recurrence of failure differing between individual parts (i.e. seemingly process-dependent). Note, that these changes and the observed failures are in line with our experience on the A31 and A80. X-AffectedPlatforms: A64-uQ7 Signed-off-by: Philipp Tomsich <>
2017-02-02sun50iw1p1: Perform power-setup before increasing operating clocksPhilipp Tomsich
Increasing the operating clocks may increase the current draw (or require a higher voltage for certain voltage rails). To ensure that we never run into a problem in this area, the initialisation sequence is reordered to first perform the PMIC setup and then reprogram the clocking. X-AffectedPlatforms: A64-uQ7 Signed-off-by: Philipp Tomsich <>
2016-11-11avoid PLL_CPUX setup on H5Andre Przywara
It hung for me without it ...
2016-11-10sunxi: add most basic H5 supportAndre Przywara
The Allwinner H5 SoC is quite close to the A64, but will mostly paired with simple I2C voltage controllers in contrast to the complex PMIC A64 boards use these days. Read the SoC ID and only initialize the PMIC when an A64 is detected. Just print the SoC name if it is an H5, the regulator does not need to be setup initially (though we may need it later).
2016-11-10sunxi: print SoC ID on startupAndre Przywara
Each Allwinner SoC contains a SoC ID, which can be used to identify a chip. Add a function to retrieve this value and print it upon initializing ATF.
2016-11-10sunxi: remove unused GPIO codeAndre Przywara
Allwinner provided code for setting up the pinmux configuration. Only that this code has no user, so we can completely remove it.
2016-11-10sunxi: power: set DRAM voltage to 1.5VAndre Przywara
On the Pine64 boards (at least on some of them) the PMIC does not reset the DRAM voltage (DCDC5) to the required 1.5V. Program the respective AXP register to improve DRAM stability.
2016-10-23sunxi: setup basic clocksAndre Przywara
Different ways of booting set up the clocks differently, so lets initialize the basic clocks here to be on the same page.
2016-10-23sunxi: fix udelay() implementationAndre Przywara
Nah, compilers are way too clever these days to fall for those simple delay loops, in fact the function resulted into a single "ret" to be generated. Use an inline assembly loop instead.
2016-10-23sun50i: CPU ops: disable delay loopsAndre Przywara
The CPU power down/up code has delays in the sequence. It turns out that the udelay() function has been optimized away by the compiler, so there is no delay in between the steps in the sequence. Moreover actually having those delays in the sequence breaks the code (the PSCI handler hangs). Until we know if and what delays are actually needed, lets change the code to be easily able to turn on and off the delays - and turn it off for now to mimic the current behaviour. This allows fixing (and reusing) the udelay() function in a next step. Signed-off-by: Andre Przywara <>
2016-08-08sunxi: power: enable DLDO4 switch as wellAndre Przywara
The DLDO4 switch enables power to the SDIO module slot, which usually carries a WiFi module. Enable this power rail unconditionally for now until we have proper regulator support. Signed-off-by: Andre Przywara <>
2016-06-02bl31: output memory location of running codeAndre Przywara
For debugging purposes it seems useful to output the part of memory that ATF is running in. Get the current location of the PC and deduct the SRAM/DRAM region we have been loaded to. Signed-off-by: Andre Przywara <>
2016-06-02sun50i: switch RSB and SRAM1 to be secure-onlyAndre Przywara
The default security setup makes all peripherals available to the non-secure world. Set the RSB (which connects to the PMIC, which is exclusively controlled by firmware) and SRAM A1 to be secure-only. This prevents accidental (or malicious) tinkering with the PMIC, which is potentially harmful to the board. NOTE: This does not seem to work as expected, since access is apparently still possile from the non-secure side. Signed-off-by: Andre Przywara <>
2016-06-02PSCI: add shutdown implementation for AXP803Andre Przywara
Now that we have the PMIC set up and directly accessible, use its power-down register to implement PSCI's SYSTEM_OFF call. Signed-off-by: Andre Przywara <>
2016-06-02sun50i: initialize and setup PMICAndre Przywara
Most boards featuring the Allwinner A64 SoC also use an AXP 803 power management IC (PMIC) to set and switch voltages. Add code to initialize Allwinner's RSB bus, which is used to talk to the PMIC more easily and faster than I2C. Then do the necessary setup, which in our case consists of enabling the DC1SW port, which powers USB and the Ethernet PHY and setting the DCDC1 voltage to 3.3V (instead of the default 3.0V). Also export the PMIC access function to be callable from the PSCI code. Signed-off-by: Andre Przywara <>
2016-06-02PSCI: remove Allwinner debug messagesAndre Przywara
Spamming the (shared) console from firmware with debug messages on (PSCI) service calls is really a bad idea, so just remove those to keep the firmware silent. Signed-off-by: Andre Przywara <>
2016-06-02bl31: remove unneeded warmreset initAndre Przywara
This code is snake oil, since we don't get any parameters passed via registers, so just remove another change to generic code. Signed-off-by: Andre Przywara <>
2016-06-02sun50i: sunxi_def.h: remove RAM layout ASCII artAndre Przywara
This information is not correct anymore, so just remove it. Signed-off-by: Andre Przywara <>
2016-06-02sun50i: platform_smp_init(): fix unneeded comments and rewrap linesAndre Przywara
Improve readability by removing comments that just repeat the code and trim the line width to fit into 80 characters. Signed-off-by: Andre Przywara <>
2016-06-02lib/aarch64: remove dead code for MMU tablesAndre Przywara
Remove pointless (because commented) code. Signed-off-by: Andre Przywara <>
2016-06-02sun50i: remove unused definitionsAndre Przywara
RAM_LOCATION_ID and friends are not used, so just remove them. Signed-off-by: Andre Przywara <>
2016-06-02bl31: revert Allwinner changes to bl31_main.cAndre Przywara
Remove those changes to the non-platform specific directory. They are pointless and platform ports should confine their code to the platform directory. Signed-off-by: Andre Przywara <>
2016-06-02sun50i: smc handlers: remove Allwinner specific service callsAndre Przywara
Allwinner provided some vendor specific services handled by ATF, which we no longer need. Also they were placed in the wrong ID range (generic ARM services) and not in the vendor specific area. The main service that gets lost is the transfer to AArch64 EL2, which we can easily do ourselves using the RMR register. Signed-off-by: Andre Przywara <>
2016-06-02sun50i: MHU, SCPI: remove codeAndre Przywara
Without the arisc we don't need client side mailboxes and SCPI support, so remove the code for that. Signed-off-by: Andre Przywara <>
2016-06-02sun50i: arisc: remove codeAndre Przywara
We no longer need and want the arisc, so remove all code that was associated with it. Signed-off-by: Andre Przywara <>
2016-06-02PSCI: remove arisc from PSCI_SHUTDOWNAndre Przywara
The arisc can tell the PMIC to power down the SoC, but we are going to loose the arisc, so replace the arisc implementation for shutdown with a warning and a hang until we have the PMIC code in place. Signed-off-by: Andre Przywara <>
2016-06-02PSCI: replace arisc call for PSCI_RESET with watchdog resetAndre Przywara
We cannot ask the arisc for help anymore, so let's program the watchdog to trigger a reset in the shortest possible time period to achieve a system reset if non-secure world requests it. Signed-off-by: Andre Przywara <>
2016-06-02PSCI: rework sun50i CPU state management to avoid the ariscAndre Przywara
Rework the SMP secondary cores bringup and shutdown to not use the arisc blob. Instead let ATF do its job and enable/disable the power clamp and further registers. Signed-off-by: Andre Przywara <>
2016-06-02sun50i: add OpenRISC stop code near BL31 start pointAndre Przywara
As ATF is now disguised as the SCP, eventually boot0 will power on the arisc and it will try to let it execute OpenRISC code. Provide some OpenRISC code to shut the core down again, by setting the shutdown bit in the PMR special register. The code sequence is: l.xor r0, r0, r0 ; clear r0 l.ori r1, r0, 0xc0 ; r1 = 0xc0 l.mtspr r0, r1, 0x4000 ; PMR(@0x4000) := r1 (0x40) Signed-off-by: Andre Przywara <>
2016-06-02bl31: remove no longer needed boot0 headerAndre Przywara
As ATF now lives in SRAM, we can't load it directly as the ATF binary anymore (it would always be loaded into DRAM then). Instead we disguise it as the SCP, which does not require a specific boot0 header. Remove all the code that was prefixing the binary with the boot0 header (which was a bit misplaced in generic code anyway). Signed-off-by: Andre Przywara <>
2016-06-02sun50i: enter U-Boot in AArch64Andre Przywara
Drop back into non-secure world into the AArch64 state now. This allows U-Boot to run in 64-bit mode, so no need to call back into the firmware to eventually launch 64-bit kernels. Signed-off-by: Andre Przywara <>
2016-06-02sun50i: remove now unused trusted mappingAndre Przywara
Without the arisc there is no need to reserve a memory mapping for later. Remove the entries from the data structure to avoid unneeded mappings. Signed-off-by: Andre Przywara <>
2016-06-02sun50i: move ATF into SRAM A2Andre Przywara
On some boards there are issues with SRAM C, so we move ATF to run from SRAM A2 for now. It actually gives us > 32KB of working space, so a debug version works here as well. SRAM A2 is documented to be secure only, which seems like a good fit for secure monitor runtime code. But apparently this is not really true, since it's still accessible for the non-secure side. Also SRAM A2 is tighly coupled to the arisc (OpenRISC controller) and thus not the ideal place to be hogged with ARM code. Signed-off-by: Andre Przywara <>
2016-06-02sun50i: move ATF into SRAM CAndre Przywara
This moves ATF from the (unsecured) DRAM into SRAM C. Not fully decided if this is the place it should eventually live, but it's better than using the beginning of DRAM for it. SRAM C could be programmed to be secure only (not done here yet). Signed-off-by: Andre Przywara <>
2016-06-02sun50i: mmap: dont map the whole device area, exclude SRAMAndre Przywara
If we soon run in SRAM, the memory mapping code maps .text & friends anyway, so we can confine the device mapping to the actual memory region used by devices. We exclude the SRAM/BROM regions. Signed-off-by: Andre Przywara <>
2016-06-02sun50i: limit ATF sizeAndre Przywara
Without the arisc we don't need any buffer memory for SCP communication anymore, so we can drastically reduce the memory footprint of ATF from 2MB to 64KB. This is needed to put ATF eventually in SRAM. Signed-off-by: Andre Przywara <>
2016-06-02sun50i: fix comment about NS_IMAGE_OFFSET locationAndre Przywara
U-Boot gets loaded at 160MB into the DRAM, not at 128MB. Signed-off-by: Andre Przywara <>
2016-06-02linking: fix LENGTH attribute in linker scriptAndre Przywara
Signed-off-by: Andre Przywara <>
2016-06-02sun50i: smc calls: remove (in)secure register read/write service callsAndre Przywara
There are two SMC calls that allowed non-secure software to read and write _every_ "register", in fact memory locations. This breaks the whole secure/non-secure separation scheme and thus has to go. Signed-off-by: Andre Przywara <>
2016-06-02assert: revert removal of assertion debug printAndre Przywara
Allwinner removed the code which prints a meaningful debug output if an assertion triggered. Revert that part to give a clue about what's wrong instead of just silently halting. Signed-off-by: Andre Przywara <>
2016-06-02sun50i: remove unneeded platform-specific GIC setupAndre Przywara
The Allwinner code defined a platform specific GIC setup. However we don't need secure IRQs or a special setup, so we can easily go with the default ARM GIC setup provided by the driver. Remove the unneeded code file, associated calls and code lines. Signed-off-by: Andre Przywara <>
2016-06-02drivers: arm_gic: remove GICv3 assertionAndre Przywara
The generic ARM GIC setup code has an assertion about a valid GICv3 redistributor base address. Remove this to allow to setup GICv2s using the generic interface. Signed-off-by: Andre Przywara <>
2016-06-02drivers: arm_gic: allow zero secure interruptsAndre Przywara
Currently the generic GIC driver code has an assert to halt if no valid pointer to the list of secure interrupts is specified. Rework this to barf only if the number of secure interrupts is greater than zero. This allows to specify zero secure interrupts and pass a NULL pointer for the table address. Signed-off-by: Andre Przywara <>