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authorEtienne Carriere <etienne.carriere@linaro.org>2017-11-15 09:26:53 +0100
committerJérôme Forissier <jerome.forissier@linaro.org>2017-11-15 10:56:15 +0100
commitcc45d720b0ec5c1db806e7e620515aacd4a2143f (patch)
tree00ea75eb5e6bfd4fd1259a872b2d45b15478fdd7 /.shippable.yml
parent5762c0a71de265219095052b53cc735add963b19 (diff)
core: pager can use memory between SRAM start and core load address
If core is loaded some 4kB pages above the start of the physical internal ram, some 4kB memory block will not be used by the pager. This situation can occur if the beginning of the internal ram is used by a bootloader. Bootloader must load op-tee above its own used memory. Such bootloader memory is freely available to op-tee core (pager). This change adds the physical memory between TEE RAM base address and the op-tee entry point address to the pager page pool. This change also default maps this area so that pager identifies physical pages as valid page addresses. This changes fixes the plat-vexpress against CFG_TEE_RAM_START being different from CFG_TEE_LOAD_ADDR. Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org> Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
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