core: pager can use memory between SRAM start and core load address

If core is loaded some 4kB pages above the start of the physical
internal ram, some 4kB memory block will not be used by the pager.

This situation can occur if the beginning of the internal ram is
used by a bootloader. Bootloader must load op-tee above its own
used memory. Such bootloader memory is freely available to op-tee
core (pager).

This change adds the physical memory between TEE RAM base address
and the op-tee entry point address to the pager page pool. This
change also default maps this area so that pager identifies physical
pages as valid page addresses.

This changes fixes the plat-vexpress against CFG_TEE_RAM_START being
different from CFG_TEE_LOAD_ADDR.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

3 files changed, 15 insertions, 6 deletions

diff --git a/core/arch/arm/kernel/generic_boot.c b/core/arch/arm/kernel/generic_boot.c
index 951eb2f1..4c7cc6d4 100644
--- a/core/arch/arm/kernel/generic_boot.c
+++ b/core/arch/arm/kernel/generic_boot.c
@@ -397,13 +397,11 @@ static void init_runtime(unsigned long pageable_part)
 	tee_pager_init(mm);
 
 	/*
-	 * Claim virtual memory which isn't paged, note that there migth be
-	 * a gap between tee_mm_vcore.lo and TEE_RAM_START which is also
-	 * claimed to avoid later allocations to get that memory.
+	 * Claim virtual memory which isn't paged.
 	 * Linear memory (flat map core memory) ends there.
 	 */
-	mm = tee_mm_alloc2(&tee_mm_vcore, tee_mm_vcore.lo,
-			(vaddr_t)(__pageable_start - tee_mm_vcore.lo));
+	mm = tee_mm_alloc2(&tee_mm_vcore, VCORE_UNPG_RX_PA,
+			   (vaddr_t)(__pageable_start - VCORE_UNPG_RX_PA));
 	assert(mm);
 
 	/*
@@ -421,6 +419,15 @@ static void init_runtime(unsigned long pageable_part)
 	tee_pager_add_pages((vaddr_t)__pageable_start + init_size,
 			(pageable_size - init_size) / SMALL_PAGE_SIZE, true);
 
+	/*
+	 * There may be physical pages in TZSRAM before the core load address.
+	 * These pages can be added to the physical pages pool of the pager.
+	 * This setup may happen when a the secure bootloader runs in TZRAM
+	 * and its memory can be reused by OP-TEE once boot stages complete.
+	 */
+	tee_pager_add_pages(tee_mm_vcore.lo,
+			(VCORE_UNPG_RX_PA - tee_mm_vcore.lo) / SMALL_PAGE_SIZE,
+			true);
 }
 #else
 
diff --git a/core/arch/arm/mm/core_mmu.c b/core/arch/arm/mm/core_mmu.c
index 7fa816cb..75b6e99d 100644
--- a/core/arch/arm/mm/core_mmu.c
+++ b/core/arch/arm/mm/core_mmu.c
@@ -90,6 +90,8 @@ register_sdp_mem(CFG_TEE_SDP_MEM_BASE, CFG_TEE_SDP_MEM_SIZE);
 #endif
 
 #ifdef CFG_CORE_RWDATA_NOEXEC
+register_phys_mem_ul(MEM_AREA_TEE_RAM_RO, CFG_TEE_RAM_START,
+		     VCORE_UNPG_RX_PA - CFG_TEE_RAM_START);
 register_phys_mem_ul(MEM_AREA_TEE_RAM_RX, VCORE_UNPG_RX_PA, VCORE_UNPG_RX_SZ);
 register_phys_mem_ul(MEM_AREA_TEE_RAM_RO, VCORE_UNPG_RO_PA, VCORE_UNPG_RO_SZ);
 register_phys_mem_ul(MEM_AREA_TEE_RAM_RW, VCORE_UNPG_RW_PA, VCORE_UNPG_RW_SZ);
diff --git a/core/arch/arm/plat-vexpress/main.c b/core/arch/arm/plat-vexpress/main.c
index ec952d8b..572e4296 100644
--- a/core/arch/arm/plat-vexpress/main.c
+++ b/core/arch/arm/plat-vexpress/main.c
@@ -217,7 +217,7 @@ int psci_cpu_on(uint32_t core_id, uint32_t entry, uint32_t context_id __unused)
 	ns_entry_addrs[pos] = entry;
 	dsb_ishst();
 
-	sec_entry_addrs[pos] = CFG_TEE_RAM_START;
+	sec_entry_addrs[pos] = CFG_TEE_LOAD_ADDR;
 	dsb_ishst();
 	sev();