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The CPU power down/up code has delays in the sequence. It turns out that
the udelay() function has been optimized away by the compiler, so there
is no delay in between the steps in the sequence.
Moreover actually having those delays in the sequence breaks the code
(the PSCI handler hangs).
Until we know if and what delays are actually needed, lets change the
code to be easily able to turn on and off the delays - and turn it off
for now to mimic the current behaviour.
This allows fixing (and reusing) the udelay() function in a next step.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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The DLDO4 switch enables power to the SDIO module slot, which usually
carries a WiFi module.
Enable this power rail unconditionally for now until we have proper
regulator support.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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For debugging purposes it seems useful to output the part of memory that
ATF is running in. Get the current location of the PC and deduct the
SRAM/DRAM region we have been loaded to.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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The default security setup makes all peripherals available to the
non-secure world.
Set the RSB (which connects to the PMIC, which is exclusively controlled
by firmware) and SRAM A1 to be secure-only.
This prevents accidental (or malicious) tinkering with the PMIC, which is
potentially harmful to the board.
NOTE: This does not seem to work as expected, since access is apparently
still possile from the non-secure side.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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Now that we have the PMIC set up and directly accessible, use its
power-down register to implement PSCI's SYSTEM_OFF call.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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Most boards featuring the Allwinner A64 SoC also use an AXP 803 power
management IC (PMIC) to set and switch voltages.
Add code to initialize Allwinner's RSB bus, which is used to talk to the
PMIC more easily and faster than I2C.
Then do the necessary setup, which in our case consists of enabling the
DC1SW port, which powers USB and the Ethernet PHY and setting the DCDC1
voltage to 3.3V (instead of the default 3.0V).
Also export the PMIC access function to be callable from the PSCI code.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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Spamming the (shared) console from firmware with debug messages on (PSCI)
service calls is really a bad idea, so just remove those to keep the
firmware silent.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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This information is not correct anymore, so just remove it.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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Improve readability by removing comments that just repeat the code
and trim the line width to fit into 80 characters.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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RAM_LOCATION_ID and friends are not used, so just remove them.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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Allwinner provided some vendor specific services handled by ATF, which
we no longer need. Also they were placed in the wrong ID range (generic
ARM services) and not in the vendor specific area.
The main service that gets lost is the transfer to AArch64 EL2, which
we can easily do ourselves using the RMR register.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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Without the arisc we don't need client side mailboxes and SCPI support,
so remove the code for that.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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We no longer need and want the arisc, so remove all code that was
associated with it.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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The arisc can tell the PMIC to power down the SoC, but we are going to
loose the arisc, so replace the arisc implementation for shutdown with a
warning and a hang until we have the PMIC code in place.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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We cannot ask the arisc for help anymore, so let's program the watchdog
to trigger a reset in the shortest possible time period to achieve
a system reset if non-secure world requests it.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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Rework the SMP secondary cores bringup and shutdown to not use the arisc
blob. Instead let ATF do its job and enable/disable the power clamp and
further registers.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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Drop back into non-secure world into the AArch64 state now.
This allows U-Boot to run in 64-bit mode, so no need to call back
into the firmware to eventually launch 64-bit kernels.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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Without the arisc there is no need to reserve a memory mapping for
later. Remove the entries from the data structure to avoid unneeded
mappings.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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On some boards there are issues with SRAM C, so we move ATF to run from
SRAM A2 for now. It actually gives us > 32KB of working space, so a debug
version works here as well.
SRAM A2 is documented to be secure only, which seems like a good fit for
secure monitor runtime code. But apparently this is not really true,
since it's still accessible for the non-secure side.
Also SRAM A2 is tighly coupled to the arisc (OpenRISC controller) and
thus not the ideal place to be hogged with ARM code.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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This moves ATF from the (unsecured) DRAM into SRAM C.
Not fully decided if this is the place it should eventually live, but
it's better than using the beginning of DRAM for it.
SRAM C could be programmed to be secure only (not done here yet).
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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If we soon run in SRAM, the memory mapping code maps .text & friends
anyway, so we can confine the device mapping to the actual memory
region used by devices. We exclude the SRAM/BROM regions.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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Without the arisc we don't need any buffer memory for SCP communication
anymore, so we can drastically reduce the memory footprint of ATF
from 2MB to 64KB. This is needed to put ATF eventually in SRAM.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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U-Boot gets loaded at 160MB into the DRAM, not at 128MB.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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The Allwinner code defined a platform specific GIC setup. However
we don't need secure IRQs or a special setup, so we can easily go with
the default ARM GIC setup provided by the driver.
Remove the unneeded code file, associated calls and code lines.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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Add a function to get the highest implemented exception level and
use that for entering BL3-3 in.
Also we make the bit-size we enter non-secure world a parameter, so that
we can easily switch between AArch32 and AArch64.
(HACK: Keep entering U-Boot still in AArch32 SVC for now.)
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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sun50iw1p1.h contains a lot of register addresses and platform
specific defines, the vast majority of them both unused by the code
and also not needed for a bl31 setup.
Remove the header file and pull the actually needed definitions into
sunxi_def.h.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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The serial debug driver is hard to read. Also it uses a C struct
to describe a fixed hardware device' register layout.
Clean up the code to be more readable and switch to the usual
(BASE_ADDR + REG_OFFSET) scheme for accessing registers.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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This function does nothing, apparently it was copied from the FVP
code. Remove its definition and the call.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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Instead of commenting the routine from FVP and the call, simply
define the print_plat_interconnect_regs macros as empty, which is
the recommended way in case there is no interconnect information
available.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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We have macros to generate define and populate the memory map
structures, but in fact need only one instance for EL3, as sunxi
does not need EL1 page tables.
Remove the unneeded code.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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The TSP is just for testing a secure payload, which we don't need,
so just remove the code.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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The sun50i port only uses BL31, so there is no need for then BL1 and BL2
code files (copied from the FVP port). Remove them.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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No need to compile those code in.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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Remove dead code, unused definitions and stream-line the code.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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The topology code was apparently copied from the ARM FVP model, which
is very versatile and allows for a sophisticated, configurable topology
setup.
Allwinner SoC on the other hand are at best multi-cluster - the A64 in
fact has only one cluster.
Simplify the sunxi specific topology code to support two affinity
levels at most - this drastically reduces the code size and makes
it much more readable.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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The architected timer is hardwired to be driven by the 24 MHz clock.
Remove all code that tries to determine this dynamically.
Also fix the actual number, which is not 24 * 2^20, but 24 * 10^6 Hz.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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Add some constants to the console code to make it more readable.
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A lot of code is not needed:
- no need for empty function which have a default implementation
- no need for A57 code and Juno workarounds
- no need for specific core enumeration in a single cluster SoC
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Allwinner removed "-pedantic" from the list of CFLAGS to get away
with some conditional debug macros using a GNU extension.
Fix those macros to use a standard compliant syntax and re-enable
-pedantic.
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The Pine64 Wiki[1] links to a BSP tarball, among other things
containing a dump of an ARM Trusted Firmware source tree with
Allwinner changes on top.
Since the tarball does not contain any version history information
about the changes, this commit is just the diff between the ATF 1.0
release and the files from the Allwinner provided tarball.
The executable flag from many source has been removed.
[1] http://wiki.pine64.org/index.php/Pine_A64_Software_Release#Linux_BSP_Related
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This patch gathers miscellaneous minor fixes to the documentation, and comments
in the source code.
Change-Id: I631e3dda5abafa2d90f464edaee069a1e58b751b
Co-Authored-By: Soby Mathew <soby.mathew@arm.com>
Co-Authored-By: Dan Handley <dan.handley@arm.com>
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This patch changes the UART port assignment for various BL stages
so as to make it consistent on the platform ports. The BL1, BL2 and
BL3-1 now uses UART0 on the FVP port and SoC UART0 on the Juno port.
The BL3-2 uses UART2 on the FVP port and FPGA UART0 on the Juno
port.
This provides an interim fix to ARM-software/tf-issues#220 until
support is added for changing the UART port for a BL image between
cold boot and runtime.
Change-Id: Iae5faea90be3d59e41e597b34a902f93e737505a
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This patch removes the PRIMARY_CPU definition hardcoded in the
Juno port. Instead, the primary CPU is obtained at runtime by
reading the SCC General Purpose Register 1 (GPR_1), whose value
is copied by the SCP into shared memory during the boot process.
Change-Id: I3981daa92eb7142250712274cf7f655b219837f5
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This patch adds the Juno platform specific handlers for PSCI
SYSTEM_OFF and SYSTEM_RESET operations.
Change-Id: Ie389adead533ec2314af44d721b4d0f306147c7d
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This patch implements the TSP on Juno. It executes from on-chip Trusted
SRAM.
Also, the other bootloader images (i.e. BL1 R/W, BL2 and BL3-1) have
been moved around. The reason is, although there was enough space
overall to store the TSP in SRAM, there was no contiguous free chunk
of SRAM big enough to hold it.
This patch keeps the overall memory layout (i.e. keeping BL1 R/W at
the bottom, BL2 at the top and BL3-1 in between) but moves the base
addresses of all the bootloader images in such a way that:
- memory fragmentation is reduced enough to fit BL3-2 in;
- new base addresses are suitable for release builds as well as debug
ones;
- each image has a few extra kilobytes for future growth.
BL3-1 and BL3-2 are the images which received the biggest allocations
since they will most probably grow the most.
This patch also adds instruction synchronization barriers around the code which
handles the timer interrupt in the TSP. This ensures that the interrupt is not
acknowledged after or EOIed before it is deactivated at the peripheral.
Change-Id: I1c5b51858700027ee283ac85d18e06863a27c72e
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This patch adds support for PSCI CPU_OFF and CPU_SUSPEND APIs to the Juno port
of the ARM Trusted Firmware. The maximum affinity level that can be suspended is
the cluster level (affinity level 1). Support for suspending the system level is
not present.
Change-Id: Ie2c9da0acd7d1b0d5ac64940cdf40347153e52c8
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