sun50i: remove unneeded platform-specific GIC setup

The Allwinner code defined a platform specific GIC setup. However
we don't need secure IRQs or a special setup, so we can easily go with
the default ARM GIC setup provided by the driver.
Remove the unneeded code file, associated calls and code lines.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>

7 files changed, 11 insertions, 775 deletions

diff --git a/plat/sun50iw1p1/bl31_sunxi_setup.c b/plat/sun50iw1p1/bl31_sunxi_setup.c
index ed33797..4096353 100644
--- a/plat/sun50iw1p1/bl31_sunxi_setup.c
+++ b/plat/sun50iw1p1/bl31_sunxi_setup.c
@@ -197,7 +197,8 @@ void bl31_early_platform_setup(bl31_params_t *from_bl2,
 void bl31_platform_setup(void)
 {
 	/* Initialize the gic cpu and distributor interfaces */
-	gic_setup();
+	arm_gic_init(GICC_BASE, GICD_BASE, 0, NULL, 0);
+	arm_gic_setup();
 
 	/* Detect if this SoC is a multi-cluster one. */
 	plat_setup_topology();
diff --git a/plat/sun50iw1p1/gic_sunxi.h b/plat/sun50iw1p1/gic_sunxi.h
deleted file mode 100644
index f52bde4..0000000
--- a/plat/sun50iw1p1/gic_sunxi.h
+++ /dev/null
@@ -1,344 +0,0 @@
-/*
- * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * Redistributions of source code must retain the above copyright notice, this
- * list of conditions and the following disclaimer.
- *
- * Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * Neither the name of ARM nor the names of its contributors may be used
- * to endorse or promote products derived from this software without specific
- * prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef __GIC_SUNXI_H_
-#define __GIC_SUNXI_H_
-
-
-#include "sunxi_def.h"
-/*irq num*/
-#define GIC_SRC_SPI(_n)                (32 + (_n))
-#define AW_IRQ_UART0                   GIC_SRC_SPI(0)  /* 32 */
-#define AW_IRQ_UART1                   GIC_SRC_SPI(1)  /* 33 */
-#define AW_IRQ_UART2                   GIC_SRC_SPI(2)  /* 34 */
-#define AW_IRQ_UART3                   GIC_SRC_SPI(3)  /* 35 */
-#define AW_IRQ_UART4                   GIC_SRC_SPI(4)  /* 36 */
-
-#define AW_IRQ_TWI0                    GIC_SRC_SPI(6)  /* 38 */
-#define AW_IRQ_TWI1                    GIC_SRC_SPI(7)  /* 39 */
-#define AW_IRQ_TWI2                    GIC_SRC_SPI(8)  /* 40 */
-
-#define AW_IRQ_PBEINT                  GIC_SRC_SPI(11)  /* 43 */
-#define AW_IRQ_OWA                     GIC_SRC_SPI(12)  /* 44*/
-#define AW_IRQ_DAUDIO0                 GIC_SRC_SPI(13)  /* 45 */
-#define AW_IRQ_DAUDIO1                 GIC_SRC_SPI(14)  /* 46 */
-#define AW_IRQ_DAUDIO2                 GIC_SRC_SPI(15)  /* 47 */
-
-#define AW_IRQ_PG_EINT                 GIC_SRC_SPI(17)  /* 49 */
-#define AW_IRQ_TIMER0                  GIC_SRC_SPI(18)  /* 50 */
-#define AW_IRQ_TIMER1                  GIC_SRC_SPI(19)  /* 51 */
-#define AW_IRQ_PH_EINT                 GIC_SRC_SPI(21)  /* 53 */
-
-#define AW_IRQ_WATCHDOG                GIC_SRC_SPI(25)  /* 57*/
-#define AW_IRQ_NMI                     GIC_SRC_SPI(32)  /* 64*/
-
-
-#define AW_IRQ_DMA                     GIC_SRC_SPI(50)  /* 82 */
-#define AW_IRQ_HSTIMER                 GIC_SRC_SPI(51)  /* 83 */
-#define AW_IRQ_SMC                     GIC_SRC_SPI(56)  /* 88 */
-#define AW_IRQ_MMC0                    GIC_SRC_SPI(60)  /* 92 */
-#define AW_IRQ_MMC1                    GIC_SRC_SPI(61)  /* 93 */
-#define AW_IRQ_MMC2                    GIC_SRC_SPI(62)  /* 94 */
-#define AW_IRQ_SPI0                    GIC_SRC_SPI(65)  /* 97 */
-#define AW_IRQ_SPI1                    GIC_SRC_SPI(66)  /* 98 */
-#define AW_IRQ_NAND                    GIC_SRC_SPI(70) /* 102 */
-#define AW_IRQ_USB_OTG                 GIC_SRC_SPI(71) /* 103 */
-#define AW_IRQ_USB_EHCI0               GIC_SRC_SPI(72) /* 104*/
-#define AW_IRQ_USB_OHCI0               GIC_SRC_SPI(73) /* 105 */
-#define AW_IRQ_USB_EHCI1               GIC_SRC_SPI(74) /* 106 */
-#define AW_IRQ_USB_OHCI1               GIC_SRC_SPI(75) /* 107 */
-
-#define AW_IRQ_CE0                     GIC_SRC_SPI(80) /* 112 */
-#define AW_IRQ_TS                      GIC_SRC_SPI(81) /* 113 */
-#define AW_IRQ_EMC                     GIC_SRC_SPI(82) /* 114 */
-#define AW_IRQ_SCR                     GIC_SRC_SPI(83) /* 115 */
-#define AW_IRQ_CSI                     GIC_SRC_SPI(84) /* 116 */
-#define AW_IRQ_CSI_CCI                 GIC_SRC_SPI(85) /* 117 */
-#define AW_IRQ_TCON0                   GIC_SRC_SPI(86) /* 118 */ 
-#define AW_IRQ_TCON1                   GIC_SRC_SPI(87) /* 119 */
-#define AW_IRQ_HDMI                    GIC_SRC_SPI(88) /* 120 */
-#define AW_IRQ_MIPI_DSI                GIC_SRC_SPI(89) /* 121 */
-
-#define AW_IRQ_DIT                     GIC_SRC_SPI(93) /* 125 */
-#define AW_IRQ_CE1                     GIC_SRC_SPI(94) /* 126 */
-#define AW_IRQ_DE                      GIC_SRC_SPI(95) /* 127 */
-#define AW_IRQ_ROT                     GIC_SRC_SPI(96) /* 128 */
-#define AW_IRQ_GPU_GP                  GIC_SRC_SPI(97) /* 129 */ 
-#define AW_IRQ_GPU_GPMMU               GIC_SRC_SPI(98) /* 130 */ 
-#define AW_IRQ_GPU_PP0                 GIC_SRC_SPI(99) /* 131 */ 
-#define AW_IRQ_GPU_PP0MMU              GIC_SRC_SPI(100) /* 132 */ 
-#define AW_IRQ_GPU_PMU                 GIC_SRC_SPI(101) /* 133 */ 
-#define AW_IRQ_GPU_PP1                 GIC_SRC_SPI(102) /* 134 */ 
-#define AW_IRQ_GPU_PPMMU1              GIC_SRC_SPI(103) /* 135 */ 
-
-#define AW_IRQ_CTI0                   GIC_SRC_SPI(108) /* 140 */ 
-#define AW_IRQ_CTI1                   GIC_SRC_SPI(109) /* 141 */ 
-#define AW_IRQ_CTI2                   GIC_SRC_SPI(110) /* 142 */ 
-#define AW_IRQ_CTI3                   GIC_SRC_SPI(111) /* 143 */ 
-#define AW_IRQ_COMMTX0                GIC_SRC_SPI(112) /* 144 */ 
-#define AW_IRQ_COMMTX1                GIC_SRC_SPI(113) /* 145 */ 
-#define AW_IRQ_COMMTX2                GIC_SRC_SPI(114) /* 146 */ 
-#define AW_IRQ_COMMTX3                GIC_SRC_SPI(115) /* 147 */ 
-#define AW_IRQ_COMMRX0                GIC_SRC_SPI(116) /* 148 */ 
-#define AW_IRQ_COMMRX1                GIC_SRC_SPI(117) /* 149 */ 
-#define AW_IRQ_COMMRX2                GIC_SRC_SPI(118) /* 150 */ 
-#define AW_IRQ_COMMRX3                GIC_SRC_SPI(119) /* 151 */ 
-#define AW_IRQ_PMU0                   GIC_SRC_SPI(120) /* 152 */ 
-#define AW_IRQ_PMU1                   GIC_SRC_SPI(121) /* 153 */ 
-#define AW_IRQ_PMU2                   GIC_SRC_SPI(122) /* 154 */ 
-#define AW_IRQ_PMU3                   GIC_SRC_SPI(123) /* 155 */ 
-#define AW_IRQ_AXI_ERROR              GIC_SRC_SPI(124) /*156*/
-#define GIC_IRQ_NUM                  (AW_IRQ_AXI_ERROR + 1)
-/*irq num end*/
-
-
-
-/* GIC registers */
-#define GIC_DIST_CON		(ARMA9_GIC_BASE + 0x0000)
-#define GIC_CON_TYPE		(ARMA9_GIC_BASE + 0x0004)
-#define GIC_CON_IIDR		(ARMA9_GIC_BASE + 0x0008)
-
-#define GIC_CON_IGRP(n)		(ARMA9_GIC_BASE + 0x0080 + (n)*4)
-
-#define GIC_SET_EN(_n)		(ARMA9_GIC_BASE + 0x100 + 4 * (_n))
-#define GIC_SET_EN0			GIC_SET_EN(0)	// 0x100
-#define GIC_SET_EN1			GIC_SET_EN(1)   // 0x104
-#define GIC_SET_EN2			GIC_SET_EN(2)   // 0x108
-#define GIC_SET_EN3			GIC_SET_EN(3)   // 0x10c
-#define GIC_SET_EN4			GIC_SET_EN(4)   // 0x110
-
-#define GIC_CLR_EN(_n)		(ARMA9_GIC_BASE + 0x180 + 4 * (_n))
-#define GIC_CLR_EN0			GIC_CLR_EN(0)	// 0x180
-#define GIC_CLR_EN1			GIC_CLR_EN(1)   // 0x184
-#define GIC_CLR_EN2			GIC_CLR_EN(2)   // 0x188
-#define GIC_CLR_EN3			GIC_CLR_EN(3)   // 0x18c
-#define GIC_CLR_EN4			GIC_CLR_EN(4)   // 0x190
-
-#define GIC_PEND_SET(_n)	(ARMA9_GIC_BASE + 0x200 + 4 * (_n))
-#define GIC_PEND_SET0		GIC_PEND_SET(0)	// 0x200
-#define GIC_PEND_SET1		GIC_PEND_SET(1) // 0x204
-#define GIC_PEND_SET2		GIC_PEND_SET(2) // 0x208
-#define GIC_PEND_SET3		GIC_PEND_SET(3) // 0x20c
-#define GIC_PEND_SET4		GIC_PEND_SET(4) // 0x210
-
-#define GIC_PEND_CLR(_n)	(ARMA9_GIC_BASE + 0x280 + 4 * (_n))
-#define GIC_PEND_CLR0		GIC_PEND_CLR(0)	// 0x280
-#define GIC_PEND_CLR1		GIC_PEND_CLR(1) // 0x284
-#define GIC_PEND_CLR2		GIC_PEND_CLR(2) // 0x288
-#define GIC_PEND_CLR3		GIC_PEND_CLR(3) // 0x28c
-#define GIC_PEND_CLR4		GIC_PEND_CLR(4) // 0x290
-
-#define GIC_ACT_SET(_n)		(ARMA9_GIC_BASE + 0x300 + 4 * (_n))
-#define GIC_ACT_SET0		GIC_ACT_SET(0)	// 0x300
-#define GIC_ACT_SET1		GIC_ACT_SET(1)  // 0x304
-#define GIC_ACT_SET2		GIC_ACT_SET(2)  // 0x308
-#define GIC_ACT_SET3		GIC_ACT_SET(3)  // 0x30c
-#define GIC_ACT_SET4		GIC_ACT_SET(4)  // 0x310
-
-#define GIC_ACT_CLR(_n)		(ARMA9_GIC_BASE + 0x380 + 4 * (_n))
-#define GIC_ACT_CLR0		GIC_ACT_CLR(0)	// 0x380
-#define GIC_ACT_CLR1		GIC_ACT_CLR(1)  // 0x384
-#define GIC_ACT_CLR2		GIC_ACT_CLR(2)  // 0x388
-#define GIC_ACT_CLR3		GIC_ACT_CLR(3)  // 0x38c
-#define GIC_ACT_CLR4		GIC_ACT_CLR(4)  // 0x390
-
-#define GIC_SGI_PRIO(_n)	(ARMA9_GIC_BASE + 0x400 + 4 * (_n))
-#define GIC_SGI_PRIO0		GIC_SGI_PRIO(0)	// 0x400
-#define GIC_SGI_PRIO1		GIC_SGI_PRIO(1) // 0x404
-#define GIC_SGI_PRIO2		GIC_SGI_PRIO(2) // 0x408
-#define GIC_SGI_PRIO3		GIC_SGI_PRIO(3) // 0x40C
-
-#define GIC_PPI_PRIO(_n)	(ARMA9_GIC_BASE + 0x410 + 4 * (_n))
-#define GIC_PPI_PRIO0		GIC_PPI_PRIO(0)	// 0x410
-#define GIC_PPI_PRIO1		GIC_PPI_PRIO(1) // 0x414
-#define GIC_PPI_PRIO2		GIC_PPI_PRIO(2) // 0x418
-#define GIC_PPI_PRIO3		GIC_PPI_PRIO(3) // 0x41C
-
-#define GIC_SPI_PRIO(_n)	(ARMA9_GIC_BASE + 0x420 + 4 * (_n))
-#define GIC_SPI_PRIO0		GIC_SPI_PRIO(0 )	// 0x420
-#define GIC_SPI_PRIO1 		GIC_SPI_PRIO(1 )    // 0x424
-#define GIC_SPI_PRIO2 		GIC_SPI_PRIO(2 )    // 0x428
-#define GIC_SPI_PRIO3 		GIC_SPI_PRIO(3 )    // 0x42C
-#define GIC_SPI_PRIO4 		GIC_SPI_PRIO(4 )    // 0x430
-#define GIC_SPI_PRIO5 		GIC_SPI_PRIO(5 )    // 0x434
-#define GIC_SPI_PRIO6 		GIC_SPI_PRIO(6 )    // 0x438
-#define GIC_SPI_PRIO7 		GIC_SPI_PRIO(7 )    // 0x43C
-#define GIC_SPI_PRIO8 		GIC_SPI_PRIO(8 )    // 0x440
-#define GIC_SPI_PRIO9 		GIC_SPI_PRIO(9 )    // 0x444
-#define GIC_SPI_PRIO10		GIC_SPI_PRIO(10)    // 0x448
-#define GIC_SPI_PRIO11		GIC_SPI_PRIO(11)    // 0x44C
-#define GIC_SPI_PRIO12		GIC_SPI_PRIO(12)    // 0x450
-#define GIC_SPI_PRIO13		GIC_SPI_PRIO(13)    // 0x454
-#define GIC_SPI_PRIO14		GIC_SPI_PRIO(14)    // 0x458
-#define GIC_SPI_PRIO15		GIC_SPI_PRIO(15)    // 0x45C
-#define GIC_SPI_PRIO16		GIC_SPI_PRIO(16)    // 0x460
-#define GIC_SPI_PRIO17		GIC_SPI_PRIO(17)    // 0x464
-#define GIC_SPI_PRIO18		GIC_SPI_PRIO(18)    // 0x468
-#define GIC_SPI_PRIO19		GIC_SPI_PRIO(19)    // 0x46C
-#define GIC_SPI_PRIO20		GIC_SPI_PRIO(20)    // 0x470
-#define GIC_SPI_PRIO21		GIC_SPI_PRIO(21)    // 0x474
-#define GIC_SPI_PRIO22		GIC_SPI_PRIO(22)    // 0x478
-#define GIC_SPI_PRIO23		GIC_SPI_PRIO(23)    // 0x47C
-#define GIC_SPI_PRIO24		GIC_SPI_PRIO(24)    // 0x480
-#define GIC_SPI_PRIO25		GIC_SPI_PRIO(25)    // 0x484
-#define GIC_SPI_PRIO26		GIC_SPI_PRIO(26)    // 0x488
-#define GIC_SPI_PRIO27		GIC_SPI_PRIO(27)    // 0x48C
-#define GIC_SPI_PRIO28		GIC_SPI_PRIO(28)    // 0x490
-#define GIC_SPI_PRIO29		GIC_SPI_PRIO(29)    // 0x494
-#define GIC_SPI_PRIO30		GIC_SPI_PRIO(30)    // 0x498
-#define GIC_SPI_PRIO31		GIC_SPI_PRIO(31)    // 0x49C
-
-#define GIC_SGI_PROC_TARG(_n)	(ARMA9_GIC_BASE + 0x800 + 4 * (_n))
-#define GIC_SGI_PROC_TARG0		GIC_SGI_PROC_TARG(0)	// 0x800
-#define GIC_SGI_PROC_TARG1		GIC_SGI_PROC_TARG(1)    // 0x804
-#define GIC_SGI_PROC_TARG2		GIC_SGI_PROC_TARG(2)    // 0x808
-#define GIC_SGI_PROC_TARG3		GIC_SGI_PROC_TARG(3)    // 0x80C
-
-#define GIC_PPI_PROC_TARG(_n)	(ARMA9_GIC_BASE + 0x810 + 4 * (_n))
-#define GIC_PPI_PROC_TARG0		GIC_PPI_PROC_TARG(0)	// 0x810
-#define GIC_PPI_PROC_TARG1		GIC_PPI_PROC_TARG(1)    // 0x814
-#define GIC_PPI_PROC_TARG2		GIC_PPI_PROC_TARG(2)    // 0x818
-#define GIC_PPI_PROC_TARG3		GIC_PPI_PROC_TARG(3)    // 0x81C
-
-#define GIC_SPI_PROC_TARG(_n)	(ARMA9_GIC_BASE + 0x820 + 4 * (_n))
-#define GIC_SPI_PROC_TARG0 		GIC_SPI_PROC_TARG(0 )	// 0x820
-#define GIC_SPI_PROC_TARG1 		GIC_SPI_PROC_TARG(1 )   // 0x824
-#define GIC_SPI_PROC_TARG2 		GIC_SPI_PROC_TARG(2 )   // 0x828
-#define GIC_SPI_PROC_TARG3 		GIC_SPI_PROC_TARG(3 )   // 0x82C
-#define GIC_SPI_PROC_TARG4 		GIC_SPI_PROC_TARG(4 )   // 0x830
-#define GIC_SPI_PROC_TARG5 		GIC_SPI_PROC_TARG(5 )   // 0x834
-#define GIC_SPI_PROC_TARG6 		GIC_SPI_PROC_TARG(6 )   // 0x838
-#define GIC_SPI_PROC_TARG7 		GIC_SPI_PROC_TARG(7 )   // 0x83C
-#define GIC_SPI_PROC_TARG8 		GIC_SPI_PROC_TARG(8 )   // 0x840
-#define GIC_SPI_PROC_TARG9 		GIC_SPI_PROC_TARG(9 )   // 0x844
-#define GIC_SPI_PROC_TARG10		GIC_SPI_PROC_TARG(10)   // 0x848
-#define GIC_SPI_PROC_TARG11		GIC_SPI_PROC_TARG(11)   // 0x84C
-#define GIC_SPI_PROC_TARG12		GIC_SPI_PROC_TARG(12)   // 0x850
-#define GIC_SPI_PROC_TARG13		GIC_SPI_PROC_TARG(13)   // 0x854
-#define GIC_SPI_PROC_TARG14		GIC_SPI_PROC_TARG(14)   // 0x858
-#define GIC_SPI_PROC_TARG15		GIC_SPI_PROC_TARG(15)   // 0x85C
-#define GIC_SPI_PROC_TARG16		GIC_SPI_PROC_TARG(16)   // 0x860
-#define GIC_SPI_PROC_TARG17		GIC_SPI_PROC_TARG(17)   // 0x864
-#define GIC_SPI_PROC_TARG18		GIC_SPI_PROC_TARG(18)   // 0x868
-#define GIC_SPI_PROC_TARG19		GIC_SPI_PROC_TARG(19)   // 0x86C
-#define GIC_SPI_PROC_TARG20		GIC_SPI_PROC_TARG(20)   // 0x870
-#define GIC_SPI_PROC_TARG21		GIC_SPI_PROC_TARG(21)   // 0x874
-#define GIC_SPI_PROC_TARG22		GIC_SPI_PROC_TARG(22)   // 0x878
-#define GIC_SPI_PROC_TARG23		GIC_SPI_PROC_TARG(23)   // 0x87C
-#define GIC_SPI_PROC_TARG24		GIC_SPI_PROC_TARG(24)   // 0x880
-#define GIC_SPI_PROC_TARG25		GIC_SPI_PROC_TARG(25)   // 0x884
-#define GIC_SPI_PROC_TARG26		GIC_SPI_PROC_TARG(26)   // 0x888
-#define GIC_SPI_PROC_TARG27		GIC_SPI_PROC_TARG(27)   // 0x88C
-#define GIC_SPI_PROC_TARG28		GIC_SPI_PROC_TARG(28)   // 0x890
-#define GIC_SPI_PROC_TARG29		GIC_SPI_PROC_TARG(29)   // 0x894
-#define GIC_SPI_PROC_TARG30		GIC_SPI_PROC_TARG(30)   // 0x898
-#define GIC_SPI_PROC_TARG31		GIC_SPI_PROC_TARG(31)   // 0x89C
-
-#define GIC_IRQ_MOD_CFG(_n)		(ARMA9_GIC_BASE + 0xc00 + 4 * (_n))
-#define GIC_IRQ_MOD_CFG0		GIC_IRQ_MOD_CFG(0)		// 0xc00 - SGI
-#define GIC_IRQ_MOD_CFG1		GIC_IRQ_MOD_CFG(1)  	// 0xc04 - PPI
-#define GIC_IRQ_MOD_CFG2		GIC_IRQ_MOD_CFG(2)  	// 0xc08 - SPI0 ~ 15
-#define GIC_IRQ_MOD_CFG3		GIC_IRQ_MOD_CFG(3)  	// 0xc0C - SPI16 ~ 31
-#define GIC_IRQ_MOD_CFG4		GIC_IRQ_MOD_CFG(4)  	// 0xc10 - SPI32 ~ 47
-#define GIC_IRQ_MOD_CFG5		GIC_IRQ_MOD_CFG(5)  	// 0xc14 - SPI48 ~ 63
-#define GIC_IRQ_MOD_CFG6		GIC_IRQ_MOD_CFG(6)  	// 0xc18 - SPI64 ~ 79
-#define GIC_IRQ_MOD_CFG7		GIC_IRQ_MOD_CFG(7)  	// 0xc1C - SPI80 ~ 95
-#define GIC_IRQ_MOD_CFG8		GIC_IRQ_MOD_CFG(8)  	// 0xc20 - SPI96 ~ 111
-#define GIC_IRQ_MOD_CFG9		GIC_IRQ_MOD_CFG(9)  	// 0xc24 - SPI112 ~ 127
-
-#define GIC_SOFT_IRQ_GEN		(ARMA9_GIC_BASE + 0xf00)	// 0xf00
-#define GIC_SGI_PEND_SET(_n)	(ARMA9_GIC_BASE + 0xf10 + 4 * (_n))
-#define GIC_SGI_PEND_SET0		GIC_SGI_PEND_SET(0)		// 0xf10
-#define GIC_SGI_PEND_SET1		GIC_SGI_PEND_SET(1)		// 0xf14
-#define GIC_SGI_PEND_SET2		GIC_SGI_PEND_SET(2)		// 0xf18
-#define GIC_SGI_PEND_SET3		GIC_SGI_PEND_SET(3)		// 0xf1C
-#define GIC_SGI_PEND_CLR(_n)	(ARMA9_GIC_BASE + 0xf10 + 4 * (_n))
-#define GIC_SGI_PEND_CLR0		GIC_SGI_PEND_CLR(0)		// 0xf20
-#define GIC_SGI_PEND_CLR1		GIC_SGI_PEND_CLR(1)		// 0xf24
-#define GIC_SGI_PEND_CLR2		GIC_SGI_PEND_CLR(2)		// 0xf28
-#define GIC_SGI_PEND_CLR3		GIC_SGI_PEND_CLR(3)		// 0xf2C
-
-
-#define GIC_CPU_IF_CTRL			(ARMA9_CPUIF_BASE + 0x000)	// 0x8000
-#define GIC_INT_PRIO_MASK		(ARMA9_CPUIF_BASE + 0x004) // 0x8004
-#define GIC_BINARY_POINT		(ARMA9_CPUIF_BASE + 0x008) // 0x8008
-#define GIC_INT_ACK_REG			(ARMA9_CPUIF_BASE + 0x00c) // 0x800c
-#define GIC_END_INT_REG			(ARMA9_CPUIF_BASE + 0x010) // 0x8010
-#define GIC_RUNNING_PRIO		(ARMA9_CPUIF_BASE + 0x014) // 0x8014
-#define GIC_HIGHEST_PENDINT		(ARMA9_CPUIF_BASE + 0x018) // 0x8018
-#define GIC_DEACT_INT_REG		(ARMA9_CPUIF_BASE + 0x1000)// 0x1000
-#define GIC_AIAR_REG			(ARMA9_CPUIF_BASE + 0x020) // 0x8020
-#define GIC_AEOI_REG			(ARMA9_CPUIF_BASE + 0x024) // 0x8024
-#define GIC_AHIGHEST_PENDINT	(ARMA9_CPUIF_BASE + 0x028) // 0x8028
-
-
-/* gic source list */
-/* software generated interrupt */
-#define GIC_SRC_SGI(_n)		(_n)
-#define GIC_SRC_SGI0		GIC_SRC_SGI(0 )  // (0 )
-#define GIC_SRC_SGI1        GIC_SRC_SGI(1 )  // (1 )
-#define GIC_SRC_SGI2        GIC_SRC_SGI(2 )  // (2 )
-#define GIC_SRC_SGI3        GIC_SRC_SGI(3 )  // (3 )
-#define GIC_SRC_SGI4        GIC_SRC_SGI(4 )  // (4 )
-#define GIC_SRC_SGI5        GIC_SRC_SGI(5 )  // (5 )
-#define GIC_SRC_SGI6        GIC_SRC_SGI(6 )  // (6 )
-#define GIC_SRC_SGI7        GIC_SRC_SGI(7 )  // (7 )
-#define GIC_SRC_SGI8        GIC_SRC_SGI(8 )  // (8 )
-#define GIC_SRC_SGI9        GIC_SRC_SGI(9 )  // (9 )
-#define GIC_SRC_SGI10       GIC_SRC_SGI(10)  // (10)
-#define GIC_SRC_SGI11       GIC_SRC_SGI(11)  // (11)
-#define GIC_SRC_SGI12       GIC_SRC_SGI(12)  // (12)
-#define GIC_SRC_SGI13       GIC_SRC_SGI(13)  // (13)
-#define GIC_SRC_SGI14       GIC_SRC_SGI(14)  // (14)
-#define GIC_SRC_SGI15       GIC_SRC_SGI(15)  // (15)
-/* private peripheral interrupt */
-#define GIC_SRC_PPI(_n)		(16 + (_n))
-#define GIC_SRC_PPI0		GIC_SRC_PPI(0 )  // (16)
-#define GIC_SRC_PPI1        GIC_SRC_PPI(1 )  // (17)
-#define GIC_SRC_PPI2        GIC_SRC_PPI(2 )  // (18)
-#define GIC_SRC_PPI3        GIC_SRC_PPI(3 )  // (19)
-#define GIC_SRC_PPI4        GIC_SRC_PPI(4 )  // (20)
-#define GIC_SRC_PPI5        GIC_SRC_PPI(5 )  // (21)
-#define GIC_SRC_PPI6        GIC_SRC_PPI(6 )  // (22)
-#define GIC_SRC_PPI7        GIC_SRC_PPI(7 )  // (23)
-#define GIC_SRC_PPI8        GIC_SRC_PPI(8 )  // (24)
-#define GIC_SRC_PPI9        GIC_SRC_PPI(9 )  // (25)
-#define GIC_SRC_PPI10       GIC_SRC_PPI(10)  // (26)
-#define GIC_SRC_PPI11       GIC_SRC_PPI(11)  // (27)
-#define GIC_SRC_PPI12       GIC_SRC_PPI(12)  // (28)
-#define GIC_SRC_PPI13       GIC_SRC_PPI(13)  // (29)
-#define GIC_SRC_PPI14       GIC_SRC_PPI(14)  // (30)
-#define GIC_SRC_PPI15       GIC_SRC_PPI(15)  // (31)
-/* external peripheral interrupt */
-#define GIC_SRC_SPI(_n)		(32 + (_n))
-
-
-#endif
-
diff --git a/plat/sun50iw1p1/plat_gic.c b/plat/sun50iw1p1/plat_gic.c
deleted file mode 100644
index 78e1a81..0000000
--- a/plat/sun50iw1p1/plat_gic.c
+++ /dev/null
@@ -1,402 +0,0 @@
-/*
- * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * Redistributions of source code must retain the above copyright notice, this
- * list of conditions and the following disclaimer.
- *
- * Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * Neither the name of ARM nor the names of its contributors may be used
- * to endorse or promote products derived from this software without specific
- * prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-#include <arch_helpers.h>
-#include <assert.h>
-#include <bl_common.h>
-#include <gic_v2.h>
-#include <interrupt_mgmt.h>
-#include <platform.h>
-#include <debug.h>
-#include "sunxi_def.h"
-#include "sunxi_private.h"
-#include "gic_sunxi.h"
-
-
-/* Value used to initialise Non-Secure irq priorities four at a time */
-#define DEFAULT_NS_PRIORITY_X4 \
-	(GIC_HIGHEST_NS_PRIORITY | \
-	(GIC_HIGHEST_NS_PRIORITY << 8) | \
-	(GIC_HIGHEST_NS_PRIORITY << 16) | \
-	(GIC_HIGHEST_NS_PRIORITY << 24))
-
-
-/*******************************************************************************
- * Enable secure interrupts and use FIQs to route them. Disable legacy bypass
- * and set the priority mask register to allow all interrupts to trickle in.
- ******************************************************************************/
-void gic_cpuif_setup(unsigned int gicc_base)
-{
-	unsigned int val;
-
-	gicc_write_pmr(gicc_base, GIC_PRI_MASK);
-
-	val = ENABLE_GRP0 | FIQ_EN;
-	val |= FIQ_BYP_DIS_GRP0 | IRQ_BYP_DIS_GRP0;
-	val |= FIQ_BYP_DIS_GRP1 | IRQ_BYP_DIS_GRP1;
-	gicc_write_ctlr(gicc_base, val);
-}
-
-/*******************************************************************************
- * Place the cpu interface in a state where it can never make a cpu exit wfi as
- * as result of an asserted interrupt. This is critical for powering down a cpu
- ******************************************************************************/
-void gic_cpuif_deactivate(unsigned int gicc_base)
-{
-	unsigned int val;
-
-	/* Disable secure, non-secure interrupts and disable their bypass */
-	val = gicc_read_ctlr(gicc_base);
-	val &= ~(ENABLE_GRP0 | ENABLE_GRP1);
-	val |= FIQ_BYP_DIS_GRP1 | FIQ_BYP_DIS_GRP0;
-	val |= IRQ_BYP_DIS_GRP0 | IRQ_BYP_DIS_GRP1;
-	gicc_write_ctlr(gicc_base, val);
-}
-
-void gic_set_secure(unsigned int gicd_base, unsigned id)
-{
-	/* Set interrupt as Group 0 */
-	gicd_clr_igroupr(gicd_base, id);
-
-	/* Set priority to max */
-	gicd_set_ipriorityr(gicd_base, id, GIC_HIGHEST_SEC_PRIORITY);
-}
-
-#if 0
-/*******************************************************************************
- * Per cpu gic distributor setup which will be done by all cpus after a cold
- * boot/hotplug. This marks out the secure interrupts & enables them.
- ******************************************************************************/
-void gic_pcpu_distif_setup(unsigned int gicd_base)
-{
-	unsigned i;
-
-	/* Mark all 32 PPI interrupts as Group 1 (non-secure) */
-	mmio_write_32(gicd_base + GICD_IGROUPR, 0xffffffffu);
-
-	/* Setup PPI priorities doing four at a time */
-	for (i = 0; i < 32; i += 4)
-		mmio_write_32(gicd_base + GICD_IPRIORITYR + i, DEFAULT_NS_PRIORITY_X4);
-
-	/* Configure those PPIs we want as secure, and enable them. */
-	static const char sec_irq[] = {
-		IRQ_SEC_PHY_TIMER,
-		IRQ_SEC_SGI_0,
-		IRQ_SEC_SGI_1,
-		IRQ_SEC_SGI_2,
-		IRQ_SEC_SGI_3,
-		IRQ_SEC_SGI_4,
-		IRQ_SEC_SGI_5,
-		IRQ_SEC_SGI_6,
-		IRQ_SEC_SGI_7
-	};
-	for (i = 0; i < sizeof(sec_irq) / sizeof(sec_irq[0]); i++) {
-		gic_set_secure(gicd_base, sec_irq[i]);
-		gicd_set_isenabler(gicd_base, sec_irq[i]);
-	}
-}
-
-/*******************************************************************************
- * Global gic distributor setup which will be done by the primary cpu after a
- * cold boot. It marks out the secure SPIs, PPIs & SGIs and enables them. It
- * then enables the secure GIC distributor interface.
- ******************************************************************************/
-static void gic_distif_setup(unsigned int gicd_base)
-{
-	unsigned int i, ctlr;
-	const unsigned int ITLinesNumber =
-				gicd_read_typer(gicd_base) & IT_LINES_NO_MASK;
-
-	/* Disable the distributor before going further */
-	ctlr = gicd_read_ctlr(gicd_base);
-	ctlr &= ~(ENABLE_GRP0 | ENABLE_GRP1);
-	gicd_write_ctlr(gicd_base, ctlr);
-
-	/* Mark all lines of SPIs as Group 1 (non-secure) */
-	for (i = 0; i < ITLinesNumber; i++)
-		mmio_write_32(gicd_base + GICD_IGROUPR + 4 + i * 4, 0xffffffffu);
-
-	/* Setup SPI priorities doing four at a time */
-	for (i = 0; i < ITLinesNumber * 32; i += 4)
-		mmio_write_32(gicd_base + GICD_IPRIORITYR + 32 + i, DEFAULT_NS_PRIORITY_X4);
-
-	/* Configure the SPIs we want as secure */
-	static const char sec_irq[] = {
-		IRQ_MHU,
-		IRQ_GPU_SMMU_0,
-		IRQ_GPU_SMMU_1,
-		IRQ_ETR_SMMU,
-		IRQ_TZC400,
-		IRQ_TZ_WDOG
-	};
-	for (i = 0; i < sizeof(sec_irq) / sizeof(sec_irq[0]); i++)
-		gic_set_secure(gicd_base, sec_irq[i]);
-
-	/* Route watchdog interrupt to this CPU and enable it. */
-	gicd_set_itargetsr(gicd_base, IRQ_TZ_WDOG,
-			   platform_get_core_pos(read_mpidr()));
-	gicd_set_isenabler(gicd_base, IRQ_TZ_WDOG);
-
-	/* Now setup the PPIs */
-	gic_pcpu_distif_setup(gicd_base);
-
-	/* Enable Group 0 (secure) interrupts */
-	gicd_write_ctlr(gicd_base, ctlr | ENABLE_GRP0);
-}
-#endif
-
-#define writel(v,a) mmio_write_32((a),(v))
-
-void gic_distributor_init(uint32_t addr)
-{
-	uint32_t cpumask = 0x01010101;
-	uint32_t gic_irqs;
-	uint32_t i;
-	
-	writel(0, GIC_DIST_CON);
-	/* check GIC hardware configutation */
-	gic_irqs = ((mmio_read_32(GIC_CON_TYPE) & 0x1f) + 1) * 32;
-	if (gic_irqs > 1020)
-	{
-		gic_irqs = 1020;
-	}
-	if (gic_irqs < GIC_IRQ_NUM)
-	{
-		NOTICE("GIC parameter config error, only support %d"
-				" irqs < %d(spec define)!!\n", gic_irqs, GIC_IRQ_NUM);
-		return ;
-	}
-
-	/*  Set ALL interrupts as group1(non-secure) interrupts */
-	for (i=1; i<GIC_IRQ_NUM; i+=16)
-	{
-	    writel(0xffffffff, GIC_CON_IGRP(i>>4));
-	}
-
-	
-	/* set trigger type to be level-triggered, active low */
-	for (i=0; i<GIC_IRQ_NUM; i+=16)
-	{
-		writel(0, GIC_IRQ_MOD_CFG(i>>4));
-	}
-	/* set priority */
-	for (i=GIC_SRC_SPI(0); i<GIC_IRQ_NUM; i+=4)
-	{
-		writel(0xa0a0a0a0, GIC_SPI_PRIO((i-32)>>2));
-	}
-	/* set processor target */
-	for (i=32; i<GIC_IRQ_NUM; i+=4)
-	{
-		writel(cpumask, GIC_SPI_PROC_TARG((i-32)>>2));
-	}
-	/* disable all interrupts */
-	for (i=32; i<GIC_IRQ_NUM; i+=32)
-	{
-		writel(0xffffffff, GIC_CLR_EN(i>>5));
-	}
-	/* clear all interrupt active state */
-	for (i=32; i<GIC_IRQ_NUM; i+=32)
-	{
-		writel(0xffffffff, GIC_ACT_CLR(i>>5));
-	}
-	
-	writel(3, GIC_DIST_CON);
-
-
-	return ;
-}
-/*
-************************************************************************************************************
-*
-*                                             function
-*
-*    name          :
-*
-*    parmeters     :
-*
-*    return        :
-*
-*    note          :
-*
-*
-************************************************************************************************************
-*/
-void gic_cpuif_init(uint32_t addr)
-{
-	uint32_t i;
-
-	writel(0, GIC_CPU_IF_CTRL);
-	/*
-	 * Deal with the banked PPI and SGI interrupts - disable all
-	 * PPI interrupts, ensure all SGI interrupts are enabled.
-	*/
-	writel(0xffff0000, GIC_CLR_EN(0));
-	writel(0x0000ffff, GIC_SET_EN(0));
-	/* Set priority on PPI and SGI interrupts */
-	for (i=0; i<16; i+=4)
-	{
-		writel(0xa0a0a0a0, GIC_SGI_PRIO(i>>2));
-	}
-	for (i=16; i<32; i+=4)
-	{
-		writel(0xa0a0a0a0, GIC_PPI_PRIO((i-16)>>2));
-	}
-
-	writel(0xf0, GIC_INT_PRIO_MASK);
-
-	writel(0xb, GIC_CPU_IF_CTRL);
-
-	return ;
-}
-
-void gic_pcpu_distif_setup(unsigned int gicd_base)
-{
-	int i ;
-	/* Mark all 32 PPI interrupts as Group 1 (non-secure) */
-	mmio_write_32(gicd_base + GICD_IGROUPR, 0xffffffffu);
-
-	/* Setup PPI priorities doing four at a time */
-	for (i = 0; i < 32; i += 4)
-		mmio_write_32(gicd_base + GICD_IPRIORITYR + i, 0xa0a0a0a0);
-}
-
-void gic_setup(void)
-{
-	gic_cpuif_init(GICC_BASE);
-	gic_distributor_init(GICD_BASE);
-}
-
-/*******************************************************************************
- * An ARM processor signals interrupt exceptions through the IRQ and FIQ pins.
- * The interrupt controller knows which pin/line it uses to signal a type of
- * interrupt. The platform knows which interrupt controller type is being used
- * in a particular security state e.g. with an ARM GIC, normal world could use
- * the GICv2 features while the secure world could use GICv3 features and vice
- * versa.
- * This function is exported by the platform to let the interrupt management
- * framework determine for a type of interrupt and security state, which line
- * should be used in the SCR_EL3 to control its routing to EL3. The interrupt
- * line is represented as the bit position of the IRQ or FIQ bit in the SCR_EL3.
- ******************************************************************************/
-uint32_t plat_interrupt_type_to_line(uint32_t type, uint32_t security_state)
-{
-	assert(type == INTR_TYPE_S_EL1 ||
-	       type == INTR_TYPE_EL3 ||
-	       type == INTR_TYPE_NS);
-
-	assert(sec_state_is_valid(security_state));
-
-	/*
-	 * We ignore the security state parameter because Juno is GICv2 only
-	 * so both normal and secure worlds are using ARM GICv2.
-	 */
-	return gicv2_interrupt_type_to_line(GICC_BASE, type);
-}
-
-/*******************************************************************************
- * This function returns the type of the highest priority pending interrupt at
- * the GIC cpu interface. INTR_TYPE_INVAL is returned when there is no
- * interrupt pending.
- ******************************************************************************/
-uint32_t plat_ic_get_pending_interrupt_type(void)
-{
-	uint32_t id;
-
-	id = gicc_read_hppir(GICC_BASE);
-
-	/* Assume that all secure interrupts are S-EL1 interrupts */
-	if (id < 1022)
-		return INTR_TYPE_S_EL1;
-
-	if (id == GIC_SPURIOUS_INTERRUPT)
-		return INTR_TYPE_INVAL;
-
-	return INTR_TYPE_NS;
-}
-
-/*******************************************************************************
- * This function returns the id of the highest priority pending interrupt at
- * the GIC cpu interface. INTR_ID_UNAVAILABLE is returned when there is no
- * interrupt pending.
- ******************************************************************************/
-uint32_t plat_ic_get_pending_interrupt_id(void)
-{
-	uint32_t id;
-
-	id = gicc_read_hppir(GICC_BASE);
-
-	if (id < 1022)
-		return id;
-
-	if (id == 1023)
-		return INTR_ID_UNAVAILABLE;
-
-	/*
-	 * Find out which non-secure interrupt it is under the assumption that
-	 * the GICC_CTLR.AckCtl bit is 0.
-	 */
-	return gicc_read_ahppir(GICC_BASE);
-}
-
-/*******************************************************************************
- * This functions reads the GIC cpu interface Interrupt Acknowledge register
- * to start handling the pending interrupt. It returns the contents of the IAR.
- ******************************************************************************/
-uint32_t plat_ic_acknowledge_interrupt(void)
-{
-	return gicc_read_IAR(GICC_BASE);
-}
-
-/*******************************************************************************
- * This functions writes the GIC cpu interface End Of Interrupt register with
- * the passed value to finish handling the active interrupt
- ******************************************************************************/
-void plat_ic_end_of_interrupt(uint32_t id)
-{
-	gicc_write_EOIR(GICC_BASE, id);
-}
-
-/*******************************************************************************
- * This function returns the type of the interrupt id depending upon the group
- * this interrupt has been configured under by the interrupt controller i.e.
- * group0 or group1.
- ******************************************************************************/
-uint32_t plat_ic_get_interrupt_type(uint32_t id)
-{
-	uint32_t group;
-
-	group = gicd_get_igroupr(GICD_BASE, id);
-
-	/* Assume that all secure interrupts are S-EL1 interrupts */
-	if (group == GRP0)
-		return INTR_TYPE_S_EL1;
-	else
-		return INTR_TYPE_NS;
-}
diff --git a/plat/sun50iw1p1/plat_pm.c b/plat/sun50iw1p1/plat_pm.c
index f4f4e29..56329db 100644
--- a/plat/sun50iw1p1/plat_pm.c
+++ b/plat/sun50iw1p1/plat_pm.c
@@ -30,6 +30,7 @@
 
 #include <assert.h>
 #include <arch_helpers.h>
+#include <arm_gic.h>
 #include <debug.h>
 #include <errno.h>
 #include <platform.h>
@@ -118,24 +119,12 @@ int32_t sunxi_affinst_on_finish(uint64_t mpidr, uint32_t afflvl, uint32_t state)
 	if (sunxi_do_plat_actions(afflvl, state) == -EAGAIN)
 		return PSCI_E_SUCCESS;
 
-
-	/*
-	 * Perform the common cluster specific operations i.e enable coherency
-	 * if this cluster was off.
-	 */
-	if (afflvl != MPIDR_AFFLVL0)
-	{
-		//cci_enable_cluster_coherency(mpidr);
-	}
-
 	// set smp bit before cache enable
 	platform_smp_init();
 
 	/* Enable the gic cpu interface */
-	gic_cpuif_setup(GICC_BASE);
-
-	/* Sunxi todo: Is this setup only needed after a cold boot? */
-	gic_pcpu_distif_setup(GICD_BASE);
+	arm_gic_cpuif_setup();
+	arm_gic_pcpu_distif_setup();
 
 	return PSCI_E_SUCCESS;
 }
@@ -191,7 +180,7 @@ static int32_t sunxi_power_down_common(uint32_t afflvl, uint64_t mpidr, uint64_t
 	uint32_t cluster_state = arisc_power_on;
 
 	/* Prevent interrupts from spuriously waking up this cpu */
-	gic_cpuif_deactivate(GICC_BASE);
+	arm_gic_cpuif_deactivate();
 
 	/* Cluster is to be turned off, so disable coherency */
 	if (afflvl > MPIDR_AFFLVL0) {
@@ -266,7 +255,8 @@ static int32_t sunxi_affinst_suspend_finish(uint64_t mpidr,
 					   uint32_t state)
 {
 	if ((afflvl == psci_get_suspend_afflvl()) && ((mpidr & 0xff) == 0x0)) {
-		gic_setup();
+		arm_gic_init(GICC_BASE, GICD_BASE, 0, NULL, 0);
+		arm_gic_setup();
 		console_init(SUNXI_UART0_BASE, UART0_CLK_IN_HZ, UART0_BAUDRATE);
 		arisc_cpux_ready_notify();
 
diff --git a/plat/sun50iw1p1/platform.mk b/plat/sun50iw1p1/platform.mk
index 3a1d1e5..720c543 100644
--- a/plat/sun50iw1p1/platform.mk
+++ b/plat/sun50iw1p1/platform.mk
@@ -70,13 +70,14 @@ PLAT_BL_COMMON_SOURCES	:= lib/aarch64/xlat_tables.c			\
 
 
 
-BL31_SOURCES		+=	drivers/arm/cci400/cci400.c \
+BL31_SOURCES		+=	drivers/arm/gic/arm_gic.c		\
 				drivers/arm/gic/gic_v2.c		\
+				drivers/arm/gic/gic_v3.c		\
 				lib/cpus/aarch64/cortex_a53.S		\
+				plat/common/plat_gic.c			\
 				plat/common/aarch64/platform_mp_stack.S	\
 				plat/sun50iw1p1/bl31_sunxi_setup.c	\
 				plat/sun50iw1p1/plat_pm.c		\
-				plat/sun50iw1p1/plat_gic.c		\
 				plat/sun50iw1p1/mhu.c			\
 				plat/sun50iw1p1/scpi.c			\
 				plat/sun50iw1p1/sunxi_security.c	\
diff --git a/plat/sun50iw1p1/sunxi_def.h b/plat/sun50iw1p1/sunxi_def.h
index d24e3de..8bd9ea3 100644
--- a/plat/sun50iw1p1/sunxi_def.h
+++ b/plat/sun50iw1p1/sunxi_def.h
@@ -47,9 +47,6 @@
 #define GICD_BASE			0x01c81000
 #define GICC_BASE			0x01c82000
 
-#define ARMA9_GIC_BASE  		GICD_BASE
-#define ARMA9_CPUIF_BASE		GICC_BASE
-
 /* Firmware Image Package */
 #define FIP_IMAGE_NAME			"fip.bin"
 #define SUNXI_PRIMARY_CPU			0x0
diff --git a/plat/sun50iw1p1/sunxi_private.h b/plat/sun50iw1p1/sunxi_private.h
index 3dc5ced..434f91d 100644
--- a/plat/sun50iw1p1/sunxi_private.h
+++ b/plat/sun50iw1p1/sunxi_private.h
@@ -34,13 +34,6 @@
 #include <bl_common.h>
 #include <platform_def.h>
 
-
-void gic_cpuif_deactivate(unsigned int gicc_base);
-void gic_cpuif_setup(unsigned int gicc_base);
-void gic_pcpu_distif_setup(unsigned int gicd_base);
-void gic_setup(void);
-
-
 typedef volatile struct mailbox {
 	unsigned long value
 	__attribute__((__aligned__(CACHE_WRITEBACK_GRANULE)));