diff options
| author | Andre Przywara <andre.przywara@arm.com> | 2016-05-02 00:50:00 +0100 |
|---|---|---|
| committer | Andre Przywara <andre.przywara@arm.com> | 2016-06-02 01:29:47 +0100 |
| commit | 633933c3d56932e6ddb54bcc2ac904f3fec206d3 (patch) | |
| tree | a2ac37e8a5308b69ab3fbf277db0347988eabf48 /plat | |
| parent | b0ff32bc4142aecfb71234c602e9bd4b1c020ebb (diff) | |
sun50i: add OpenRISC stop code near BL31 start point
As ATF is now disguised as the SCP, eventually boot0 will power on
the arisc and it will try to let it execute OpenRISC code.
Provide some OpenRISC code to shut the core down again, by setting
the shutdown bit in the PMR special register.
The code sequence is:
l.xor r0, r0, r0 ; clear r0
l.ori r1, r0, 0xc0 ; r1 = 0xc0
l.mtspr r0, r1, 0x4000 ; PMR(@0x4000) := r1 (0x40)
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Diffstat (limited to 'plat')
0 files changed, 0 insertions, 0 deletions