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2016-09-18sun9i: improved clock setup for better boot reliabilityPhilipp Tomsich
2016-09-18ARM: sunxi: non-DM-interface for sunxi SPIPhilipp Tomsich
2016-09-18ARM: sun6i: spi: implements SPI driverOctav Zlatior
The driver currently only supports sun6i. Signed-off-by: Octav Zlatior <octav.zlatior@theobroma-systems.com>
2016-09-18sun9i: Adjust clock-setup to match what Allwinner used in U-BootPhilipp Tomsich
Our initial clock setup had been based on the basic_bootloader (boot0), but differed from what Allwinner used in their SDK in 'u-boot-2011.09'. To improve compatibility, we now switch to the same clocking they have used. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2016-09-18sunxi: Support chip-id reading on sun9i (A80)Philipp Tomsich
The chip-id on the sun9i resides in the SID block, but at an offset from what we'd expect with older variants.
2016-09-18pmic: add DM driver for the AXP806 and AXP809Philipp Tomsich
2016-09-18sunxi: Add support for the AXP806 on sun9iPhilipp Tomsich
On A80 boards, both a AXP809 (primary) and AXP806 (secondary) PMIC are found. The AXP806 supplies the Cortex-A15 cores with a poly-phase supply to deliver up to 10A of total power. When used in the slave configuration, the AXP806 needs a write to the REGADDR_EXT register to configure it to work on the same RSB bus as the primary PMIC.
2016-09-18sunxi: support the AXP809 PMIC (for A80 platforms)Philipp Tomsich
Implement support for the AXP809 PMIC that is used on A80 platforms as the primary PMIC and powers most peripherals and the CPUA (Cortex-A7) cluster. A AXP806 is usually the slave PMIC, which will provide the power for the CPUB (Cortex-A15) cluster. The default voltage settings have been chosen to be safe values for a Optimus, Cubieboard and A80-Q7. These changes are validated against the A80-Q7 module.
2016-09-18dm: pmic: wrap RSB into dm driverPhilipp Tomsich
Implement driver to wrap RSB in a device-model I2C driver.
2016-09-18ARM: sun9i: increase CONFIG_SPL_MAX_SIZEPhilipp Tomsich
some older compilers generate less than compact code we thus use 32KB (of 40KB) for SPL
2016-09-18sunxi: always compile as THUMB for sun9iPhilipp Tomsich
2016-09-18sunxi: enable SPL for sun9iPhilipp Tomsich
2016-09-18sunxi: add initial clock setup for sun9i for SPLPhilipp Tomsich
2016-09-18sunxi: mark SDC2 on sun9i (A80) as capable of 8-bit modePhilipp Tomsich
2016-09-18mmc: call MMC reset before probing for MMC after failed SD probePhilipp Tomsich
2016-09-18sunxi: issue a MMC hardware reset on core_initPhilipp Tomsich
2016-09-18sunxi: add MMC pinmux setup for SDC2 on sun9iPhilipp Tomsich
2016-09-18sunxi: Do not define CONFIG_PHY_ADDR for SUNXI_GMACPhilipp Tomsich
We can not define CONFIG_PHY_ADDR in sunxi-common.h, as this will break devices that have a different PHY_ADDR and rely on the PHY address autodetection (phy_find_by_mask) to detect the address.
2016-09-18sunxi: Support GbE controller (GMAC) for sun9i (A80)Philipp Tomsich
* board/sunxi/gmac.c(eth_init_board): Add support for configuring sun9i (A80) for Ethernet support in RGMII mode. * arch/arm/include/asm/arch-sunxi/gpio.h (SUN9I_GPA_GMAC): Define. * arch/arm/include/asm/arch-sunxi/clock_sun9i.h: Add Ethernet support for sun9i (A80), defining struct sunxi_sysctl_reg (which contains the GMAC clock control on sun9i) and AHB_{GATE,RESET}_OFFSET_GMAC * arch/arm/include/asm/arch-sunxi/cpu_sun9i.h(SUNXI_SYSCTL_BASE): Define. * arch/arm/dts/sun9i-a80.dtsi: add device-tree support for GMAC on sun9i (A80).
2016-09-18sunxi: Support UART4 on A80 (sun9i) as system consolePhilipp Tomsich
* arch/arm/cpu/armv7/sunxi/board.c (gpio_init): Configure UART4 pins and function for CONFIG_CONS_INDEX == 5 (UART4) on CONFIG_MACH_SUN9I * include/configs/sunxi-common.h: Define CONFIG_SYS_NS16550_COM5 and CONFIG_SYS_NS16550_COM6 for CONFIG_MACH_SUN9I to refer to UART4 and UART5, respectively. Define OF_STDOUT_PATH for CONFIG_CONS_INDEX == 5 (UART4) on CONFIG_MACH_SUN9I * arch/arm/include/asm/arch-sunxi/gpio.h (SUN9I_GPG_UART4): Define. Validated against A80-Q7 module.
2016-09-18sunxi: Enable SMP mode for sun9i (A80)Philipp Tomsich
2016-09-18sunxi: add gtbus-initialisation for sun9iPhilipp Tomsich
On sun9i, the GTBUS manages transaction priority and bandwidth for multiple read ports when accessing DRAM. The initialisation mirrors the settings from Allwinner's boot0 for now, even though this may not be optimal for all applications (e.g. headless systems might want to give priority to IO modules). Adding a common callout to gtbus_init() from the SPL clock init with a weakly defined implementation in sunxi/clock.c to fallback to for platforms that don't require this.
2016-09-18sunxi: DRAM initialisation for sun9iPhilipp Tomsich
This adds DRAM initialisation code for sun9i, which calculates the appropriate timings based on timing information for the supplied DDR3 bin and the clock speeds used. With this DRAM setup, we have verified DDR3 clocks of up to 792MHz (i.e. DDR3-1600) on the A80-Q7 using a dual-channel configuration.
2016-09-18usb: gadget: Move CONFIG_USB_GADGET to KconfigSam Protsenko
The description was borrowed from kernel. "tristate" type was changed to "bool" (I believe we don't support modules for u-boot yet, right?). CONFIG_USB_GADGET requires CONFIG_USB to be defined too, so add it along as well. Definitions were added to defconfig files in a way that "make savedefconfig" generates exactly the same file as used defconfig. Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> [trini: Add zynq_zc702 conversion] Signed-off-by: Tom Rini <trini@konsulko.com>
2016-09-18tools: kwboot: Add xmodem timeout optionKevin Smith
Add command-line specification of xmodem timeout. If the binary header needs to take a while to do something (e.g. DDR ECC scrubbing), the xmodem transfer can time out. Add a configurable xmodem block timeout to allow transfers with slow binary headers to succeed. Signed-off-by: Kevin Smith <kevin.smith@elecsyscorp.com> Cc: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
2016-09-18tools: kwboot: Clean up usage textKevin Smith
Usage text was getting unwieldy and somewhat incorrect. The usage summary implied that some options were mutually exclusive (e.g. -q or -s). Clean up the summary to just include the important ones, and include a generic "[OPTIONS]" instead. Signed-off-by: Kevin Smith <kevin.smith@elecsyscorp.com> Cc: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
2016-09-18arm: mvebu: db-88f6820: Drop obsolete binary.0 placeholderAndreas Färber
It has been superseded in kwbimage.cfg in favor of an SPL in commit 9e30b31d20f0b793465d07f056b3d9885f578c0d (arm: mvebu: db-88f6820: Add SPL support with DDR init code). Found via code review. Cc: Stefan Roese <sr@denx.de> Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Stefan Roese <sr@denx.de>
2016-09-18arm: mvebu: theadorable: Add StratixV FPGA programming supportStefan Roese
This patch adds support for Altera StratixV bitstream programming. 2 FPGAs are connected to the SPI busses. This patch uses board specific write code to program the bitstream via SPI direct write mode. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr> Signed-off-by: Stefan Roese <sr@denx.de>
2016-09-18arm: mvebu: spi.h: Add registers for direct write accessStefan Roese
The direct write config register is needed for SPI direct write mode configuration. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr> Signed-off-by: Stefan Roese <sr@denx.de>
2016-09-18arm: mvebu: Add some SPI CS attributesStefan Roese
These attribute defines may be used to map an area of memory for direct access to the specific SPI devices. See SPI Direct Access Mode for further information. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr> Signed-off-by: Stefan Roese <sr@denx.de>
2016-09-18fpga: altera: Add StratixV supportStefan Roese
This patch adds support for programming of the StratixV FPGAs. Programming is done in this case (board theadorable) via SPI. The board may provide board specific code for bitstream programming. This StratixV support will be used by the theadorable board. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Tom Rini <trini@konsulko.com> Signed-off-by: Stefan Roese <sr@denx.de>
2016-09-18gpio: Add DM GPIO driver for Marvell MVEBUStefan Roese
This patch adds a DM GPIO driver for the Marvell MVEBU SoCs. There are other non-DM drivers that might be used on these platforms. But this patch creates a new DM driver. Which will be used by all Armada XP/38x boards. Other MVEBU SoC (Kirkwood / Orion) may follow once they support DM as well. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Dirk Eibach <dirk.eibach@gdsys.cc> Cc: Phil Sutter <phil@nwl.cc> Cc: Kevin Smith <kevin.smith@elecsyscorp.com> Cc: Luka Perkov <luka.perkov@sartura.hr> Cc: Tom Rini <trini@konsulko.com> Reviewed-by: Kevin Smith <kevin.smith@elecsyscorp.com> Tested-by: Kevin Smith <kevin.smith@elecsyscorp.com> Signed-off-by: Stefan Roese <sr@denx.de>
2016-09-18arm: mvebu: Fix ddr3_init() cpu configDirk Eibach
Armada 38x has a maximum of two cores. Probably copy/paste bug from Armada XP. Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc> Signed-off-by: Stefan Roese <sr@denx.de>
2016-09-18ARM: sheevaplug: correct nand partition layoutPeter Korsgaard
Commit 1e3d640316 (ARM: sheevaplug: redefine MTDPARTS) changed the partition layout (without any description why), but didn't change the offset/size to load the kernel from or the root=/dev/mtdblockX in the bootargs. The 3MB forseen for a kernel is furthermore too little. A 4.4 build of mvebu_v5_defconfig is 3.6MB: -rw-r--r-- 1 peko peko 3.6M Jan 16 20:24 uImage.kirkwood-sheevaplug When device tree support for sheevaplug was added to the kernel in commit ee514b381e (ARM: Kirkwood: Add dts files for Sheevaplug and eSATA Sheevaplug) a default flash partition layout (used if mtdparts= isn't passed on the command line / CONFIG_MTD_CMDLINE_PARTS isn't enabled) with 1MB for u-boot / environment, 4MB for the kernel and the rest for the rootfs, so use that layout here and adjust the kernel loading to match. Signed-off-by: Peter Korsgaard <peter@korsgaard.com> Signed-off-by: Stefan Roese <sr@denx.de>
2016-09-18sunxi: A83T: fix 32bit overflow warningvishnupatekar
In mctl_channel_init, (0x50<<26) which overflows 32bit. It was supposed to be 0x50<<16,corrected now. Reported-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2016-09-18sunxi: Select CONFIG_OF_BOARD_SETUP from arch/arm/KconfigHans de Goede
Always select OF_BOARD_SETUP on sunxi, rather then having it in almost all our defconfigs. This also fixes it missing from some recently added defconfigs. This commit also modifies our ft_board_setup() to not cause warnings when CONFIG_VIDEO_DT_SIMPLEFB is not set, since we will now always build it. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
2016-09-18sunxi: sinovoip-bpi-m3: drop LDO settings from defconfigvishnupatekar
Kconfig default settings are same as mentioned Sinovoip Bpi-m3 schematic. As axp818 ALDO support is enabled, it causes bpi-m3 fail to boot if ALDOs are set to 0. Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2016-09-18sunxi: Specify SATAPWR pin for Orangepi PlusHans de Goede
This enables the use of the sata connector in u-boot. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
2016-09-18sunxi: Turn satapwr on from board_initHans de Goede
There are 2 reasons for doing this: 1) The main reason for doing this is to move it outside of board/sunxi/ahci.c, so that it can be used on boards which use a usb<->sata chip too; 2) While doing this I realized that doing it from board_init also meant doing it much earlier. Some printf get_timer(0) calls show that the time between board_init() and scsi_init() is more then 600 ms, so we can drop the mdelay(500) While at it also drop the printf("SUNXI SCSI INIT\n") AHCI init is noisy enough by itself. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
2016-09-18sunxi: Fix gmac not working due to cpu_eth_init no longer being calledHans de Goede
cpu_eth_init is no longer called for dm enabled eth drivers, this was causing the sunxi gmac eth controller to no longer work in u-boot. This commit fixes this by calling the clock, reset and pinmux setup function from s_init() and enabling the phy power pin (if any) from board_init(). The enabling of phy power cannot be done from s_init because it uses dm and dm is not ready yet at this point. Note that the mdelay is dropped as the phy gets enabled much earlier now, so it is no longer needed. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk> Tested-by: Karsten Merker <merker@debian.org> Tested-by: Michael Haas <haas@computerlinguist.org>
2016-09-18sunxi: Fix 2nd usb controller on sun4i/sun7i no longer workingHans de Goede
The 2nd usb controller on sun4i/sun7i has its base address 0x8000 bytes from the 1st one, rather then 0x1000. Also the ahb clk gates are interleaved with the ohci clk-gates introducing a hole between the clks for usb1 and usb2. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
2016-09-18sunxi: Enable support for the eMMC found on the orangepi plusHans de Goede
This enables support for the eMMC found on the orangepi plus. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
2016-09-18spl: Print from which mmc slot spl is trying to bootHans de Goede
On some sunxi boards (and presumably also non sunxi boards) u-boot can be either loaded from a sdcard in a micro-sd slot, or from eMMC. Print which MMC spl tries to boot from, to help debugging. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2016-09-18sunxi: Add a bunch of missing compatible strings to sunxi_gpio.cHans de Goede
The kernel has different compatible strings for the pio block because the pin-muxing is different on all the different SoCs, but sunxi_gpio.c only support the basic gpio functionality, which is identical everywhere. Add the missing compatible strings for various SoC models. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
2016-09-18sunxi: Specify USB vbus pins for orangepi boardsHans de Goede
This fixes the USB ports not working on the orangepi_plus and stops us from messing with gpio-s which we should not touch on the orangepi_pc. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
2016-09-18sunxi: Add support for USB vbus pin for USB3Hans de Goede
The H3 has USB0 - USB3, add support for having a USB vbus pin for USB3. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
2016-09-18sunxi: Enable realtek phy supportHans de Goede
Enable building of drivers/net/phy/realtek.c so that realtek phys get properly initialized. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
2016-09-18sunxi: Enable composite video out on the CHIPAlex Kaplan
The CHIP has a composite video output in the mini-Jack connector, alongside with the 2 audio channels. Enable this output in U-Boot. Signed-off-by: Alex Kaplan <kaplan2539@gmail.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2016-09-18sunxi: Fix DCDC2 output in CHIP_defconfigBoris Brezillon
Unlike the datasheet recommendation, the R8 SoC requires a 1.4V supply for its CPU when operating at 1Ghz. Rely on the default value specified in the Kconfig entry. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2016-09-18sunxi: Configure only LVDS pins instead of all LCD pins when LVDS interface ↵Lawrence Yu
selected The behavior before this patch would attempt to configure the mux setting for pins 0 to 27 on PORTD to all be setting 3 for LVDS. The LVDS interface actually only uses pins 18 to 27 and not pins 0 to 27 as in the parallel LCD interface. This patch restricts the configuration to only the relevant pins 18 to 27 on PORTD. This was tested on a sun8i A33 tablet with an LVDS screen. MMC1 has the capability to use pins 2 to 7 on PORTD and the mux on those pins was being inadvertently set to setting 3 for MMC functionality which this patch corrects. Signed-off-by: Lawrence Yu <lyu@micile.com> [hdegoede@redhat.com: Only apply this change to A23 / A33] Signed-off-by: Hans de Goede <hdegoede@redhat.com>
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