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authorPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>2016-04-07 23:49:56 +0200
committerKlaus Goger <klaus.goger@theobroma-systems.com>2016-09-18 13:45:14 +0200
commit3107262b564318ef55bb5e308fe18a9edff08c80 (patch)
treeb87cd1069583fdf063fe17da40768ace8f82bc98
parent7406394fa0c53875235c19cb42b8942d8b491e05 (diff)
sunxi: issue a MMC hardware reset on core_init
-rw-r--r--arch/arm/include/asm/arch-sunxi/mmc.h8
-rw-r--r--drivers/mmc/sunxi_mmc.c5
2 files changed, 10 insertions, 3 deletions
diff --git a/arch/arm/include/asm/arch-sunxi/mmc.h b/arch/arm/include/asm/arch-sunxi/mmc.h
index 3da360b177..0c13872551 100644
--- a/arch/arm/include/asm/arch-sunxi/mmc.h
+++ b/arch/arm/include/asm/arch-sunxi/mmc.h
@@ -35,16 +35,18 @@ struct sunxi_mmc {
u32 cbcr; /* 0x48 CIU byte count */
u32 bbcr; /* 0x4c BIU byte count */
u32 dbgc; /* 0x50 debug enable */
- u32 res0[11];
+ u32 res0[9];
+ u32 hwrst; /* 0x78 eMMC hardware reset register */
+ u32 res1; /* 0x7c */
u32 dmac; /* 0x80 internal DMA control */
u32 dlba; /* 0x84 internal DMA descr list base address */
u32 idst; /* 0x88 internal DMA status */
u32 idie; /* 0x8c internal DMA interrupt enable */
u32 chda; /* 0x90 */
u32 cbda; /* 0x94 */
- u32 res1[26];
+ u32 res2[26];
#ifdef CONFIG_SUNXI_GEN_SUN6I
- u32 res2[64];
+ u32 res3[64];
#endif
u32 fifo; /* 0x100 / 0x200 FIFO access address */
};
diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c
index 7b33094d84..4a7dbed043 100644
--- a/drivers/mmc/sunxi_mmc.c
+++ b/drivers/mmc/sunxi_mmc.c
@@ -255,7 +255,12 @@ static int sunxi_mmc_core_init(struct mmc *mmc)
/* Reset controller */
writel(SUNXI_MMC_GCTRL_RESET, &mmchost->reg->gctrl);
+ do { /* spin */ } while (readl(&mmchost->reg->gctrl) & SUNXI_MMC_GCTRL_RESET);
+
+ /* Toggle RST output */
+ writel(0, &mmchost->reg->hwrst);
udelay(1000);
+ writel(1, &mmchost->reg->hwrst);
return 0;
}