| Age | Commit message (Collapse) | Author |
|---|
|
Add scalar instructions for parallel bit deposit and extract, with
built-in function support.
[gcc]
2020-05-11 Kelvin Nilsen <kelvin@gcc.gnu.org>
* config/rs6000/rs6000-builtin.def (__builtin_pdepd): New built-in
function.
(__builtin_pextd): Likewise.
* config/rs6000/rs6000.md (UNSPEC_PDEPD): New constant.
(UNSPEC_PEXTD): Likewise.
(pdepd): New insn.
(pextd): Likewise.
* doc/extend.texi (Basic PowerPC Built-in Functions Available for
a Future Architecture): Add descriptions of __builtin_pdepd and
__builtin_pextd functions.
[gcc/testsuite]
2020-05-11 Kelvin Nilsen <kelvin@gcc.gnu.org>
* gcc.target/powerpc/pdep-0.c: New.
* gcc.target/powerpc/pdep-1.c: New.
* gcc.target/powerpc/pextd-0.c: New.
* gcc.target/powerpc/pextd-1.c: New.
|
|
Add support for new scalar instructions for counting leading or
trailing zeros under control of a bitmask.
[gcc]
2020-05-11 Kelvin Nilsen <kelvin@gcc.gnu.org>
* config/rs6000/rs6000-builtin.def (__builtin_cntlzdm): New
built-in function definition.
(__builtin_cnttzdm): Likewise.
* config/rs6000/rs6000.md (UNSPEC_CNTLZDM): New constant.
(UNSPEC_CNTTZDM): Likewise.
(cntlzdm): New insn.
(cnttzdm): Likewise.
* doc/extend.texi (Basic PowerPC Built-in Functions available for
a Future Architecture): Add descriptions of __builtin_cntlzdm and
__builtin_cnttzdm functions.
[gcc/testsuite]
2020-05-11 Kelvin Nilsen <kelvin@gcc.gnu.org>
* gcc.target/powerpc/cntlzdm-0.c: New test.
* gcc.target/powerpc/cntlzdm-1.c: New test.
* gcc.target/powerpc/cnttzdm-0.c: New test.
* gcc.target/powerpc/cnttzdm-1.c: New test.
|
|
Add the centifuge-doubleword instruction and built-in access.
[gcc]
2020-05-11 Kelvin Nilsen <kelvin@gcc.gnu.org>
* config/rs6000/rs6000-builtin.def (BU_FUTURE_MISC_0): New
#define.
(BU_FUTURE_MISC_1): Likewise.
(BU_FUTURE_MISC_2): Likewise.
(BU_FUTURE_MISC_3): Likewise.
(__builtin_cfuged): New built-in function definition.
* config/rs6000/rs6000.md (UNSPEC_CFUGED): New constant.
(cfuged): New insn.
* doc/extend.texi (Basic PowerPC Built-in Functions Available for
a Future Architecture): New subsubsection.
[gcc/testsuite]
2020-05-11 Kelvin Nilsen <kelvin@gcc.gnu.org>
* gcc.target.powerpc/cfuged-0.c: New test.
* gcc.target.powerpc/cfuged-1.c: New test.
|
|
setnbc[r] is like setbc[r], but it writes -1 instead of 1 to the GPR.
2020-05-07 Segher Boessenkool <segher@kernel.crashing.org>
* config/rs6000/rs6000.md (*setnbc_<un>signed_<GPR:mode>): New
define_insn.
(*setnbcr_<un>signed_<GPR:mode>): New define_insn.
(*neg_eq_<mode>): Avoid for TARGET_FUTURE; add missing && 1.
(*neg_ne_<mode>): Likewise.
|
|
New instructions setbc and setbcr. setbc sets a GPR to 1 if some
condition register bit is set, and 0 otherwise; setbcr does it the
other way around.
2020-05-07 Segher Boessenkool <segher@kernel.crashing.org>
* config/rs6000/rs6000.md (setbc_<un>signed_<GPR:mode>): New
define_insn.
(*setbcr_<un>signed_<GPR:mode>): Likewise.
(cstore<mode>4): Use setbc[r] if available.
(<code><GPR:mode><GPR2:mode>2_isel): Avoid for TARGET_FUTURE.
(eq<mode>3): Use setbc for TARGET_FUTURE.
(*eq<mode>3): Avoid for TARGET_FUTURE.
(ne<mode>3): Replace :P with :GPR; use setbc for TARGET_FUTURE;
else for non-Pmode, use gen_eq and gen_xor.
(*ne<mode>3): Avoid for TARGET_FUTURE.
(*eqsi3_ext<mode>): Avoid for TARGET_FUTURE; fix missing && 1.
|
|
The emulation of mffsl with mffs, used when !TARGET_P9_MISC, is going
through the motions, but not storing the result in the given
operands[0]; it rather modifies operands[0] without effect. It also
creates a DImode pseudo that it doesn't use, overwriting subregs
instead.
The patch below fixes all of these, the indentation and a typo.
I'm concerned about several issues in the mffsl testcase. First, I
don't see that comparing the values as doubles rather than as long
longs is desirable. These are FPSCR bitfields, not FP numbers. I
understand mffs et al use double because they output to FP registers,
and the bit patterns are subnormal FP numbers, so it works, but given
the need for bit masking of at least one side, I'm changing the
compare to long longs.
Another issue with the test is that, if the compare fails, it calls
mffsl again to print the value, as if it would yield the same result.
But part of the FPSCR that mffsl (emulated with mffs or not) copies to
the output FP register is the FPCC, so the fcmpu used to compare the
result of the first mffsl will modify FPSCR and thus the result of the
second mffsl call. After changing the compare, this is no longer the
case, but I still think it's better to make absolutely sure what we
print is what we compared.
Yet another issue is that the test assumed the mffs bits that are not
to be extracted by mffsl to be already zero, instead of masking them
out explicitly. This is not about the mffs emulation in the mffsl
implementation, but about the mffs use in the test proper. The bits
appear to be zero indeed, as the bits left out are for sticky
exceptions, but there are reserved parts of FPSCR that might turn out
to be set in the future, so we're better off masking them out
explicitly, otherwise those bits could cause the compare to fail.
If some future mffsl is changed so that it copies additional nonzero
bits, the test will fail, and then we'll have a chance to adjust it
and the emulation.
for gcc/ChangeLog
PR target/94812
* gcc/config/rs6000/rs6000.md (rs6000_mffsl): Copy result to
output operand in emulation. Don't overwrite pseudos.
for gcc/testsuite/ChangeLog
PR target/94812
* gcc.target/powerpc/test_mffsl.c: Call mffsl only once.
Reinterpret the doubles as long longs for compares. Mask out
mffs bits that are not expected from mffsl.
|
|
The example code in the PR uses r2 (the TOC register) directly. In the
RTL generated for that, r2 is copied to some pseudo, and then cprop
propagates that into a "*tocref<mode>" insn, because nothing is
preventing it from doing that.
So, put the same condition in the insn condition for this as we will
later encounter in the constraint anyway, fixing this.
2020-04-01 Segher Boessenkool <segher@kernel.crashing.org>
PR target/94420
* config/rs6000/rs6000.md (*tocref<mode> for P): Add insn condition
on operands[1].
|
|
-mlongcall -mno-pltseq is supposed to emit long calls by using
indirect calls. It differs from -mlongcall -mpltseq in that the
function addresses are not placed in the PLT and thus lazy PLT
resolution is not available, affecting programs that dlopen shared
libraries.
In the case of -mcpu=future -mpcrel -mlongcall -mno-pltseq we see an
indirect call being generated, but combine merrily optimises the
sequence back to a direct call. call_indirect_pcrel is enough like
call_nonlocal_aix that this can happen.
This patch puts the call cookie back in the call rtl, removed by git
commit f90f960ca8, in order to disable the optimisation for long
calls. When that is done for call_local_aix the pattern becomes the
same as call_local32/64, so I merged them. The only difference
besides mode between call_local32 and call_local64, dating back to
1998 commit a260abc996, is that call_local64 has TARGET_64BIT in the
predicate. That alone doesn't seem reason enough to need separate
patterns; The P mode iterator selects DI on TARGET_64BIT anyway.
* config/rs6000/rs6000.c (rs6000_call_aix): Emit cookie to pattern.
(rs6000_indirect_call_template_1): Adjust to suit.
* config/rs6000/rs6000.md (call_local): Merge call_local32,
call_local64, and call_local_aix.
(call_value_local): Simlarly.
(call_nonlocal_aix, call_value_nonlocal_aix): Adjust rtl to suit,
and disable pattern when CALL_LONG.
(call_indirect_aix, call_value_indirect_aix): Adjust rtl.
(call_indirect_elfv2, call_indirect_pcrel): Likewise.
(call_value_indirect_elfv2, call_value_indirect_pcrel): Likewise.
|
|
The PLT is volatile. On PowerPC it is a bss style section which the
dynamic loader initialises to point at resolver stubs (called glink on
PowerPC64) to support lazy resolution of function addresses. The
first call to a given function goes via the dynamic loader symbol
resolver, which updates the PLT entry for that function and calls the
function. The second call, if there is one and we don't have a
multi-threaded race, will use the updated PLT entry and thus avoid
the relatively slow symbol resolver path.
Calls via the PLT are like calls via a function pointer, except that
no initialised function pointer is volatile like the PLT. All
initialised function pointers are resolved at program startup to point
at the function or are left as NULL. There is no support for lazy
resolution of any user visible function pointer.
So why does any of this matter to gcc? Well, normally the PLT call
mechanism happens entirely behind gcc's back, but since we implemented
inline PLT calls (effectively putting the PLT code stub that loads the
PLT entry inline and making that code sequence scheduled), the load of
the PLT entry is visible to gcc. That load then is subject to gcc
optimization, for example in
/* -S -mcpu=future -mpcrel -mlongcall -O2. */
int foo (int);
void bar (void)
{
while (foo(0))
foo (99);
}
we see the PLT load for foo being hoisted out of the loop and stashed
in a call-saved register. If that happens to be the first call to
foo, then the stashed value is that for the resolver stub, and every
call to foo in the loop will then go via the slow resolver path. Not
a good idea. Also, if foo turns out to be a local function and the
linker replaces the PLT calls with direct calls to foo then gcc has
just wasted a call-saved register.
This patch teaches gcc that the PLT loads are volatile. The change
doesn't affect other loads of function pointers and thus has no effect
on normal indirect function calls. Note that because the
"optimization" this patch prevents can only occur over function calls,
the only place gcc can stash PLT loads is in call-saved registers or
in other memory. I'm reasonably confident that this change will be
neutral or positive for the "ld -z now" case where the PLT is not
volatile, in code where there is any register pressure. Even if gcc
could be taught to recognise cases where the PLT is resolved, you'd
need to discount use of registers to cache PLT loads by some factor
involving the chance that those calls would be converted to direct
calls.
PR target/94145
* config/rs6000/rs6000.c (rs6000_longcall_ref): Use unspec_volatile
for PLT16_LO and PLT_PCREL.
* config/rs6000/rs6000.md (UNSPEC_PLT16_LO, UNSPEC_PLT_PCREL): Remove.
(UNSPECV_PLT16_LO, UNSPECV_PLT_PCREL): Define.
(pltseq_plt16_lo_, pltseq_plt_pcrel): Use unspec_volatile.
|
|
As PR93047 said, __builtin_apply/__builtin_return does not work well with
-frename-registers. This is caused by return register(e.g. r3) is used to
rename another register, before return register is stored to stack.
This patch fix this issue by emitting clobber for those egisters which
maybe changed by untyped call.
gcc/
2020-02-17 Jiufu Guo <guojiufu@linux.ibm.com>
PR target/93047
* config/rs6000/rs6000.md (untyped_call): Add emit_clobber.
gcc/testsuite
2020-02-17 Jiufu Guo <guojiufu@linux.ibm.com>
PR target/93047
* gcc.dg/torture/stackalign/builtin-return-2.c: New test case.
|
|
2020-02-11 Michael Meissner <meissner@linux.ibm.com>
* config/rs6000/predicates.md (cint34_operand): Rename the
-mprefixed-addr option to be -mprefixed.
* config/rs6000/rs6000-cpus.def (ISA_FUTURE_MASKS_SERVER): Rename
the -mprefixed-addr option to be -mprefixed.
(OTHER_FUTURE_MASKS): Likewise.
(POWERPC_MASKS): Likewise.
* config/rs6000/rs6000.c (rs6000_option_override_internal): Rename
the -mprefixed-addr option to be -mprefixed. Change error
messages to refer to -mprefixed.
(num_insns_constant_gpr): Rename the -mprefixed-addr option to be
-mprefixed.
(rs6000_legitimate_offset_address_p): Likewise.
(rs6000_mode_dependent_address): Likewise.
(rs6000_opt_masks): Change the spelling of "-mprefixed-addr" to be
"-mprefixed" for target attributes and pragmas.
(address_to_insn_form): Rename the -mprefixed-addr option to be
-mprefixed.
(rs6000_adjust_insn_length): Likewise.
* config/rs6000/rs6000.h (FINAL_PRESCAN_INSN): Rename the
-mprefixed-addr option to be -mprefixed.
(ASM_OUTPUT_OPCODE): Likewise.
* config/rs6000/rs6000.md (prefixed insn attribute): Rename the
-mprefixed-addr option to be -mprefixed.
* config/rs6000/rs6000.opt (-mprefixed): Rename the
-mprefixed-addr option to be prefixed. Change the option from
being undocumented to being documented.
* doc/invoke.texi (RS/6000 and PowerPC Options): Document the
-mprefixed option. Update the -mpcrel documentation to mention
-mprefixed.
|
|
From-SVN: r279813
|
|
2019-12-12 Michael Meissner <meissner@linux.ibm.com>
* config/rs6000/predicates.md (add_operand): Allow eI constants.
* config/rs6000/rs6000.md (add<mode>3): Add alternative to
generate PADDI for 34-bit constants if -mcpu=future.
From-SVN: r279476
|
|
2019-12-17 Michael Meissner <meissner@linux.ibm.com>
* config/rs6000/rs6000.md (movsi_internal1): Add alternative to
use PLI to load up 32-bit constants if -mcpu=future.
From-SVN: r279475
|
|
2019-12-17 Michael Meissner <meissner@linux.ibm.com>
* config/rs6000/rs6000.c (num_insns_constant_gpr): Return 1 if the
constant can be loaded with PLI if -mcpu=future.
* config/rs6000/rs6000.md (movdi_internal64): Add alternative to
use PLI to load up 34-bit constants if -mcpu=future.
From-SVN: r279474
|
|
It turns out we still used hardcoded register numbers for the CR fields
in some cases, and they now use the wrong numbers since we renumbered
most of the registers. So let's use the symbolic names, instead.
* config/rs6000/rs6000.md (movsi_to_cr_one): Use CR0_REGNO instead of
hardcoding the (old, expired) register number.
(*mtcrfsi): Ditto.
From-SVN: r279443
|
|
This names the so far unnamed basic mfcr pattern "set<mode>_cc", and
it deletes all the others (only the ashift one ever was generated, and
even that one only once during a whole bootstrap+regtest, and that one
is questionable -- we don't cost that pattern correctly).
* config/rs6000/rs6000.md (unnamed mfcr define_insn): Name this
set<mode>_cc.
(unnamed define_insn_and_split): Delete.
(unnamed define_insn): Delete.
(unnamed define_insn): Delete.
(unnamed define_split): Delete.
From-SVN: r279127
|
|
* config/rs6000/rs6000.md (*movsi_internal1): Fix formatting. Improve
formatting.
(*movdi_internal64): Ditto.
From-SVN: r278822
|
|
We run fwprop before combine, very early even in the case of fwprop1;
and fwprop1 will change memory addressing to what it considers cheaper.
After the "common" change, it now changes the indexed store instruction
in the testcase to be to a constant address. But that is not an
improvement at all: the byte reverse instructions only exist in the
indexed form, so they will not match anymore.
This patch changes the patterns for the byte reverse instructions to
allow plain memory_operand, letting reload fix this up.
PR target/92602
* config/rs6000/rs6000.md (bswap<mode>2_load for HSI): Change the
indexed_or_indirect_operand to be memory_operand.
(bswap<mode>2_store for HSI): Ditto.
(bswapdi2_load): Ditto.
(bswapdi2_store): Ditto.
From-SVN: r278821
|
|
2019-11-26 Michael Meissner <meissner@linux.ibm.com>
* config/rs6000/rs6000.md (movdi_internal64): Reformat.
From-SVN: r278788
|
|
2019-11-27 Michael Meissner <meissner@linux.ibm.com>
* config/rs6000/rs6000.md (movsi_internal): Reformat.
From-SVN: r278787
|
|
We currently expand various floating point comparisons early, to some
sequences with cror insns and the like. This doesn't optimize well.
Change that to allow any of the 14 floating point comparisons in the
instruction stream, and split them after combine (at split1).
* config/rs6000/predicates.md (extra_insn_branch_comparison_operator):
New predicate.
* config/rs6000/rs6000-protos.h (rs6000_emit_fp_cror): New declaration.
* config/rs6000/rs6000.c (rs6000_generate_compare): Don't do anything
special for FP comparisons that need a cror instruction eventually.
(rs6000_emit_fp_cror): New function.
(rs6000_emit_sCOND): Expand all floating point comparisons to one
instruction, for normal FP modes, with HONOR_NANS.
(rs6000_emit_cbranch): Reformat.
* config/rs6000/rs6000.md (fp_rev): New iterator.
(fp_two): New iterator.
*<code><mode>_cc for fp_rev and GPR: New define_insn_and_split.
*<code><mode>_cc for fp_two and GPR: New define_insn_and_split.
*cbranch_2insn: New define_insn_and_split.
From-SVN: r278593
|
|
Also make it a parmeterized name: @cceq_{ior,rev}_compare_<mode>.
* config/rs6000/rs6000.md (cceq_ior_compare): Rename to...
(@cceq_ior_compare_<mode> for GPR): ... this. Allow GPR instead of
just SI.
(cceq_rev_compare): Rename to...
(@cceq_rev_compare_<mode> for GPR): ... this. Allow GPR instead of
just SI.
(define_split for <bd>tf_<mode>): Add SImode first argument to
gen_cceq_ior_compare.
From-SVN: r278366
|
|
C++98 does not have long long int, and does not use (unsigned) long
long int for hexadecimal literals. So let's use an ULL suffix here,
which is still not strict C++98, but which works with more compilers.
* config/rs6000/rs6000.md (rs6000_set_fpscr_drn): Use ULL on big
hexadecimal literal.
From-SVN: r278107
|
|
Supporting TLS for -mpcrel turns out to be relatively simple. The
existing TLSGD and TLSLD unspecs happily can have their GOT pointer
reg element replaced with zero, refelecting the fact that optimisation
of calls to __tls_get_addr when pc-rel won't use the GOT pointer.
Some other insns also can be reused, and just a few added.
* config/rs6000/predicates.md (unspec_tls): Allow const0_rtx for got
element of unspec vec.
* config/rs6000/rs6000.c (rs6000_legitimize_tls_address): Support
PC-relative TLS.
* config/rs6000/rs6000.md (UNSPEC_TLSTLS_PCREL): New unspec.
(tls_gd_pcrel, tls_ld_pcrel): New insns.
(tls_dtprel, tls_tprel): Set attr prefixed when tls_size is not 16.
(tls_got_tprel_pcrel, tls_tls_pcrel): New insns.
From-SVN: r278076
|
|
This patch removes !TARGET_TLS_MARKERS support. -mtls-markers (and
-mno-tls-markers) disappear as valid options too, because I figure
they haven't been used too much except by people testing the
compiler.
* config/rs6000/rs6000.opt (mtls-markers): Delete.
* config/rs6000/rs6000.h (TARGET_TLS_MARKERS): Don't define.
(IS_NOMARK_TLSGETADDR): Likewise.
* config/rs6000/rs6000-protos.h (rs6000_output_tlsargs): Delete.
* config/rs6000/rs6000.c (rs6000_output_tlsargs): Delete.
(rs6000_legitimize_tls_address): Remove !TARGET_TLS_MARKERS code.
(rs6000_call_template_1): Delete TARGET_TLS_MARKERS test and
allow other UNSPECs besides UNSPEC_TLSGD and UNSPEC_TLSLD.
(rs6000_indirect_call_template_1): Likewise.
(rs6000_pltseq_template): Likewise.
(rs6000_opt_vars): Remove "tls-markers" entry.
* config/rs6000/rs6000.md (tls_gd<bits>): Replace TARGET_TLS_MARKERS
with TARGET_ELF.
(tls_gd_high<bits>, tls_gd_low<bits>): Likewise.
(tls_ld<bits>, tls_ld_high<bits>, tls_ld_low<bits>): Likewise.
(pltseq_plt_pcrel<mode>): Likewise.
(call_value_local32): Remove IS_NOMARK_TLSGETADDR predicate test.
(call_value_local64): Likewise.
(call_value_indirect_nonlocal_sysv<mode>): Remove IS_NOMARK_TLSGETADDR
output and length attribute sub-expression.
(call_value_nonlocal_sysv<mode>),
(call_value_nonlocal_sysv_secure<mode>),
(call_value_local_aix<mode>, call_value_nonlocal_aix<mode>),
(call_value_indirect_aix<mode>, call_value_indirect_elfv2<mode>),
(call_value_indirect_pcrel<mode>): Likewise.
* doc/install.texi (powerpc-*-*): Require binutils-2.20.
* configure.ac (HAVE_AS_TLS_MARKERS): Delete test.
* configure: Regenerate.
* config.in: Regenerate.
From-SVN: r278075
|
|
2019-11-11 Michael Meissner <meissner@linux.ibm.com>
* config/rs6000/predicates.md (prefixed_memory): New predicate.
* config/rs6000/rs6000.md (stack_protect_setdi): Deal with either
address being a prefixed load/store.
(stack_protect_testdi): Deal with either address being a prefixed
load.
From-SVN: r278069
|
|
Sometimes combine wants to do a move in CCFPmode, but we don't currently
handle moves in any CC mode other than CCmode. Fix that oversight.
* config/rs6000/rs6000.md (CC_any): New mode iterator.
(*movcc_internal1): Rename to...
(*movcc_<mode> for CC_any): ... this. Support moves of all CC modes.
From-SVN: r278017
|
|
To support full condition reduction vectorization, we have to define
vec_cmp* and vcond_mask_*. This patch is to add related expands.
Also add the missing vector fp comparison RTL pattern supports
like: ungt, unge, unlt, unle, ne, lt and le.
gcc/ChangeLog
2019-11-08 Kewen Lin <linkw@gcc.gnu.org>
PR target/92132
* config/rs6000/predicates.md
(signed_or_equality_comparison_operator): New predicate.
(unsigned_or_equality_comparison_operator): Likewise.
* config/rs6000/rs6000.md (one_cmpl<mode>2): Remove expand.
(one_cmpl<mode>3_internal): Rename to one_cmpl<mode>2.
* config/rs6000/vector.md
(vcond_mask_<mode><mode> for VEC_I and VEC_I): New expand.
(vec_cmp<mode><mode> for VEC_I and VEC_I): Likewise.
(vec_cmpu<mode><mode> for VEC_I and VEC_I): Likewise.
(vcond_mask_<mode><VEC_int> for VEC_F): New expand for float
vector modes and same-size integer vector modes.
(vec_cmp<mode><VEC_int> for VEC_F): Likewise.
(vector_lt<mode> for VEC_F): New expand.
(vector_le<mode> for VEC_F): Likewise.
(vector_ne<mode> for VEC_F): Likewise.
(vector_unge<mode> for VEC_F): Likewise.
(vector_ungt<mode> for VEC_F): Likewise.
(vector_unle<mode> for VEC_F): Likewise.
(vector_unlt<mode> for VEC_F): Likewise.
(vector_uneq<mode>): Expose name.
(vector_ltgt<mode>): Likewise.
(vector_unordered<mode>): Likewise.
(vector_ordered<mode>): Likewise.
gcc/testsuite/ChangeLog
2019-11-08 Kewen Lin <linkw@gcc.gnu.org>
PR target/92132
* gcc.target/powerpc/pr92132-fp-1.c: New test.
* gcc.target/powerpc/pr92132-fp-2.c: New test.
* gcc.target/powerpc/pr92132-int-1.c: New test.
* gcc.target/powerpc/pr92132-int-2.c: New test.
From-SVN: r277947
|
|
2019-10-23 Michael Meissner <meissner@linux.ibm.com>
* config/rs6000/rs6000-protos.h (rs6000_adjust_insn_length): New
declaration.
* config/rs6000/rs6000.c (rs6000_insn_cost): Use num_insns insn
attribute if it exists, rather than the insn size. If we use the
insn size, adjust the size to remove the extra size that prefixed
instructions take.
(rs6000_adjust_insn_length): New function.
* config/rs6000/rs6000.h (ADJUST_INSN_LENGTH): New target hook to
update the instruction sized if prefixed instructions are used.
* config/rs6000/rs6000.md (prefixed_length attribute): Delete.
(non_prefixed_length attribute): Delete.
(num_insns attribute): New insn attribute to return the number of
instructions.
(max_prefixed_insns attribute): New insn attribute to return the
maximum number of prefixed instructions in an insn.
(length attribute): Do not adjust for prefix instructions here,
punt to ADJUST_INSN_LENGTH.
(mov<mode>_64bit): Set max_prefixed_insns and num_insns.
(movtd_64bit_nodm): Set max_prefixed_insns and num_insns.
(mov<mode>_ppc64): Set max_prefixed_insns and num_insns.
* config/rs6000/vsx.md: (vsx_mov<mode>_64bit): Set
max_prefixed_insns and num_insns.
From-SVN: r277352
|
|
bottom 2 bits are non-zero.
2019-10-23 Michael Meissner <meissner@linux.ibm.com>
* config/rs6000/rs6000.md (mov<mode>_64bit_dm): Reformat.
(movtd_64bit_nodm): Reformat.
(mov<mode>_32bit): Reformat.
(mov<mode>_softfloat): Reformat.
(FMOVE128_GPR splitter): Reformat.
(DIFD splitter): Reformat.
(TI2 splitter): Reformat.
* config/rs6000/predicates.md (lwa_operand): If the bottom two
bits of the offset for the memory address are non-zero, use PLWA
if prefixed instructions are available.
From-SVN: r277349
|
|
Removes a comment that's no longer relevant.
gcc/ChangeLog:
2019-10-19 Iain Sandoe <iain@sandoe.co.uk>
* config/rs6000/rs6000.md: Delete out--of-date comment about
special-casing integer loads.
From-SVN: r277201
|
|
The current Darwin load/store lo_sum patterns have neither predicate nor
constraint. This means that most parts of the backend, which rely on
recog() to validate the rtx, can produce invalid combinations/selections.
For 32bit cases this isn't a problem since we can load/store to unaligned
addresses using D-mode insns.
Conversely, for 64bit instructions that use DS mode, this can manifest as
assemble errors (for an assembler that checks the LO14 relocations), or as
crashes caused by wrong offsets (or worse, wrong content for the two LSBs).
What we want to check for "Y" on Darwin is:
- that the alignment of the Symbols' target is sufficient for DS mode
- that the offset is suitable for DS mode.
(while looking through the Mach-O PIC unspecs).
So, the patch removes the Darwin-specific lo_sum patterns (we begin using
the movdi_internal64 patterns). We also we need to extend the handling of the
mem_operand_gpr constraint to allow looking through Mach-O PIC UNSPECs in
the lo_sum cases.
gcc/ChangeLog:
2019-10-17 Iain Sandoe <iain@sandoe.co.uk>
PR target/65342
* config/rs6000/darwin.md (movdi_low, movsi_low_st): Delete.
(movdi_low_st): Delete.
* config/rs6000/rs6000.c
(darwin_rs6000_legitimate_lo_sum_const_p): New.
(mem_operand_gpr): Validate Mach-O LO_SUM cases separately.
* config/rs6000/rs6000.md (movsi_low): Delete.
From-SVN: r277130
|
|
2019-10-02 Aaron Sawdey <acsawdey@linux.ibm.com>
* config/rs6000/rs6000-protos.h (expand_block_move): Change prototype.
* config/rs6000/rs6000-string.c (expand_block_move): Add
might_overlap parm.
* config/rs6000/rs6000.md (movmemsi): Add new pattern.
(cpymemsi): Add might_overlap parm to expand_block_move() call.
From-SVN: r276462
|
|
2019-09-30 Michael Meissner <meissner@linux.ibm.com>
* config/rs6000/predicates.md (pcrel_address): Delete predicate.
(pcrel_local_address): Replace pcrel_address predicate, use the
new function address_to_insn_form.
(pcrel_external_address): Replace with new implementation using
address_to_insn_form..
(prefixed_mem_operand): Delete predicate which is now unused.
(pcrel_external_mem_operand): Delete predicate which is now
unused.
* config/rs6000/rs6000-protos.h (enum insn_form): New
enumeration.
(enum non_prefixed): New enumeration.
(address_to_insn_form): New declaration.
(prefixed_load_p): New declaration.
(prefixed_store_p): New declaration.
(prefixed_paddi_p): New declaration.
(rs6000_asm_output_opcode): New declaration.
(rs6000_final_prescan_insn): Move declaration and update calling
signature.
(address_is_prefixed): New helper inline function.
* config/rs6000/rs6000.c(print_operand_address): Check for either
PC-relative local symbols or PC-relative external symbols.
(rs6000_emit_move): Support loading PC-relative addresses.
(mode_supports_prefixed_address_p): Delete, no longer used.
(rs6000_prefixed_address_mode_p): Delete, no longer used.
(address_to_insn_form): New function to decode an address format.
(reg_to_non_prefixed): New function to identify what the
non-prefixed memory instruction format is for a register.
(prefixed_load_p): New function to identify prefixed loads.
(prefixed_store_p): New function to identify prefixed stores.
(prefixed_paddi_p): New function to identify prefixed load
immediates.
(next_insn_prefixed_p): New static state variable.
(rs6000_final_prescan_insn): New function to determine if an insn
uses a prefixed instruction.
(rs6000_asm_output_opcode): New function to emit 'p' in front of a
prefixed instruction.
* config/rs6000/rs6000.h (FINAL_PRESCAN_INSN): New target hook.
(ASM_OUTPUT_OPCODE): New target hook.
* config/rs6000/rs6000.md (prefixed): New insn attribute for
prefixed instructions.
(prefixed_length): New insn attribute for the size of prefixed
instructions.
(non_prefixed_length): New insn attribute for the size of
non-prefixed instructions.
(pcrel_local_addr): New insn to load up a local PC-relative
address.
(pcrel_extern_addr): New insn to load up an external PC-relative
address.
(mov<mode>_64bit_dm): Split the alternatives for loading 0.0 to a
GPR and loading a 128-bit floating point type to a GPR.
From-SVN: r276300
|
|
Drop the expander and use a mode expander on the define_insn
for macho_correct_pic instead.
gcc/ChangeLog:
2019-09-27 Iain Sandoe <iain@sandoe.co.uk>
* config/rs6000/darwin.md (@macho_correct_pic_<mode>): New,
replaces the expander and two define_insn entries.
(@reload_macho_picbase_<mode>): Update gen_macho_correct_pic
call.
* config/rs6000/rs6000.md (builtin_setjmp_receiver): Likewise.
From-SVN: r276196
|
|
We can use the mode iterators directly with an @pattern to avoid the
need for an expander that was only there to pass the mode through.
gcc/ChangeLog:
2019-09-26 Iain Sandoe <iain@sandoe.co.uk>
* config/rs6000/darwin.md: Replace the expanders for
load_macho_picbase and reload_macho_picbase with use of '@'
in their respective define_insns.
(nonlocal_goto_receiver): Pass Pmode to gen_reload_macho_picbase.
* config/rs6000/rs6000-logue.c (rs6000_emit_prologue): Pass
Pmode to gen_load_macho_picbase.
* config/rs6000/rs6000.md: Likewise.
From-SVN: r276159
|
|
As a clean-up, we want to be able to use mode iterators in darwin.md.
This patch moves the include point for the Darwin include until after
the definition of the mode iterators and attrs. No functional change
intended.
gcc/ChangeLog:
2019-09-24 Iain Sandoe <iain@sandoe.co.uk>
* config/rs6000/rs6000.md: Move darwin.md include until
after the definition of the mode iterators.
From-SVN: r276106
|
|
This isn't used since 2018. (It's a remnant of paired single support).
* config/rs6000/rs6000.md (unspec): Delete UNSPEC_MV_CR_OV.
From-SVN: r275477
|
|
This isn't used since 2012. (It's a remnant of RIOS support).
* config/rs6000/rs6000.c (rs6000_rtx_costs) <case UNSPEC>: Delete.
* config/rs6000/rs6000.md (unspec): Delete UNSPEC_FRSP.
From-SVN: r275476
|
|
Every call to darn should deliver a *new* random number; such calls
should not be CSEd together. So they should be unspec_volatile, not
plain unspec.
PR target/91481
* config/rs6000/rs6000.md (unspec): Delete UNSPEC_DARN, UNSPEC_DARN_32,
and UNSPEC_DARN_RAW.
(unspecv): New enumerator values UNSPECV_DARN, UNSPECV_DARN_32, and
UNSPECV_DARN_RAW.
(darn_32): Use an unspec_volatile, and UNSPECV_DARN_32.
(darn_raw): Use an unspec_volatile, and UNSPECV_DARN_RAW.
(darn): Use an unspec_volatile, and UNSPECV_DARN.
From-SVN: r274835
|
|
* config/rs6000/altivec.md (unspec): Delete UNSPEC_DARN, UNSPEC_DARN_32,
UNSPEC_DARN_RAW, UNSPEC_CMPRB, UNSPEC_CMPRB2, UNSPEC_CMPEQB; move to...
* config/rs6000/rs6000.md (unspec): ... here.
* config/rs6000/altivec.md (darn_32, darn_raw, darn, cmprb,
*cmprb_internal, setb_signed, setb_unsigned, cmprb2, *cmprb2_internal,
cmpeqb, *cmpeqb_internal): Delete, move to...
* config/rs6000/rs6000.md (darn_32, darn_raw, darn, cmprb,
*cmprb_internal, setb_signed, setb_unsigned, cmprb2, *cmprb2_internal,
cmpeqb, *cmpeqb_internal): ... here.
From-SVN: r274834
|
|
2019-08-02 Michael Meissner <meissner@linux.ibm.com>
* config/rs6000/future.md: New file.
* config/rs6000/rs6000.md: Include future.md.
* config/rs6000/t-rs6000 (MD_INCLUDES): Add future.md.
From-SVN: r274030
|
|
This patch is part of a series that fixes ambiguous attribute
uses in .md files, i.e. cases in which attributes didn't use
<ITER:ATTR> to specify an iterator, and in which <ATTR> could
have different values depending on the iterator chosen.
No behavioural change -- produces the same code as before except
for formatting and line numbers.
2019-07-16 Richard Sandiford <richard.sandiford@arm.com>
gcc/
* config/rs6000/rs6000.md (*mov<mode>_update1): Explicitly
use <SFDF:mode>, <SFDF:MODE>, <SFDF:Ff> and <SFDF:bits> rather than
leaving the choice between SFDF and P implicit.
(*mov<mode>_update2): Likewise.
(*cmp<IBM128:mode>_internal2): Explicitly use <IBM128:MODE>
rather than leaving the choice betweem IBM128 and GPR implicit.
(*fix<uns>_trunc<IEEE128:mode><QHSI:mode>2_mem): Explicitly use
<IEEE128:MODE> rather than leaving the choice between IEEE128 and
QHSI implicit.
(AltiVec define_peephole2s): Explicitly use <ALTIVEC_DFORM:MODE>
rather than leaving the choice between ALTIVEC_DFORM and P implicit.
* config/rs6000/vsx.md
(*vsx_ext_<VSX_EXTRACT_I:VS_scalar>_fl_<FL_CONV:mode>)
(*vsx_ext_<VSX_EXTRACT_I:VS_scalar>_ufl_<FL_CONV:mode>): Explicitly
use <FL_CONV:VSisa> rather than leaving the choice between FL_CONV
and VSX_EXTRACT_I implicit.
From-SVN: r273509
|
|
It is unused.
* config/rs6000/rs6000.md (Ffre): Delete.
From-SVN: r273182
|
|
from "4" to "*" to allow the length attribute...
2019-07-03 Michael Meissner <meissner@linux.ibm.com>
* config/rs6000/altivec.md (altivec_mov<mode>, VM2 iterator):
Change the RTL attribute "length" from "4" to "*" to allow the
length attribute to be adjusted automatically for prefixed load,
store, and add immediate instructions.
* config/rs6000/rs6000.md (extendhi<mode>2, EXTHI iterator):
Likewise.
(extendsi<mode>2, EXTSI iterator): Likewise.
(movsi_internal1): Likewise.
(movsi_from_sf): Likewise.
(movdi_from_sf_zero_ext): Likewise.
(mov<mode>_internal): Likewise.
(movcc_internal1, QHI iterator): Likewise.
(mov<mode>_softfloat, FMOVE32 iterator): Likewise.
(movsf_from_si): Likewise.
(mov<mode>_hardfloat32, FMOVE64 iterator): Likewise.
(mov<mode>_softfloat64, FMOVE64 iterator): Likewise.
(mov<mode>, FMOVE128 iterator): Likewise.
(movdi_internal64): Likewise.
* config/rs6000/vsx.md (vsx_le_permute_<mode>, VSX_TI iterator):
Likewise.
(vsx_le_undo_permute_<mode>, VSX_TI iterator): Likewise.
(vsx_mov<mode>_64bit, VSX_M iterator): Likewise.
(vsx_mov<mode>_32bit, VSX_M iterator): Likewise.
(vsx_splat_v4sf): Likewise.
From-SVN: r273013
|
|
@signbit<mode>2_dm
* config/rs6000/rs6000.md (signbit<mode>2_dm): Make this a
parameterized name.
(signbit<mode>2): Use that name. Simplify.
From-SVN: r272912
|
|
@ieee_128bit_vsx_abs<mode>2
* config/rs6000/rs6000.md (ieee_128bit_vsx_abs<mode>2): Make this a
parameterized name.
(abs<mode>2): Use that name. Simplify.
From-SVN: r272907
|
|
@ieee_128bit_vsx_neg<mode>2
* config/rs6000/rs6000.md (ieee_128bit_vsx_neg<mode>2): Make this a
parameterized name.
(neg<mode>2): Use that name. Simplify.
From-SVN: r272906
|
|
@abs<mode>2_hw
* config/rs6000/rs6000.md (abs<mode>2_hw): Make this a parameterized
name.
(abs<mode>2): Use that name. Simplify.
From-SVN: r272905
|
