diff options
| author | Tom Rini <trini@konsulko.com> | 2022-07-23 13:05:12 -0400 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2022-08-04 16:18:48 -0400 |
| commit | 78475d2572615471d3c047e61481a68859d0dd7f (patch) | |
| tree | d0de486d8215feedc0eba48c2e2b4428bd66d284 | |
| parent | 7da6a9e7df2f31f35391925042f58b19c7b7d9e4 (diff) | |
Convert CONFIG_SYS_FSL_DDR_INTLV_256B to Kconfig
This converts the following to Kconfig:
CONFIG_SYS_FSL_DDR_INTLV_256B
Signed-off-by: Tom Rini <trini@konsulko.com>
26 files changed, 29 insertions, 8 deletions
@@ -413,11 +413,6 @@ The following options need to be configured: same as CONFIG_SYS_DDR_SDRAM_BASE for all Power SoCs. But it could be different for ARM SoCs. - CONFIG_SYS_FSL_DDR_INTLV_256B - DDR controller interleaving on 256-byte. This is a special - interleaving mode, handled by Dickens for Freescale layerscape - SoCs with ARM core. - CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS Number of controllers used as main memory. diff --git a/configs/ls2080aqds_SECURE_BOOT_defconfig b/configs/ls2080aqds_SECURE_BOOT_defconfig index a4143871cb..afb4e48e7e 100644 --- a/configs/ls2080aqds_SECURE_BOOT_defconfig +++ b/configs/ls2080aqds_SECURE_BOOT_defconfig @@ -56,6 +56,7 @@ CONFIG_DYNAMIC_DDR_CLK_FREQ=y CONFIG_DIMM_SLOTS_PER_CTLR=2 CONFIG_DDR_ECC=y CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y +CONFIG_SYS_FSL_DDR_INTLV_256B=y CONFIG_SYS_I2C_LEGACY=y CONFIG_SYS_I2C_EEPROM_ADDR=0x57 CONFIG_FSL_ESDHC=y diff --git a/configs/ls2080aqds_defconfig b/configs/ls2080aqds_defconfig index 91b5226585..15dadeb4e4 100644 --- a/configs/ls2080aqds_defconfig +++ b/configs/ls2080aqds_defconfig @@ -59,6 +59,7 @@ CONFIG_DYNAMIC_DDR_CLK_FREQ=y CONFIG_DIMM_SLOTS_PER_CTLR=2 CONFIG_DDR_ECC=y CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y +CONFIG_SYS_FSL_DDR_INTLV_256B=y CONFIG_SYS_I2C_LEGACY=y CONFIG_SYS_I2C_EEPROM_ADDR=0x57 CONFIG_FSL_ESDHC=y diff --git a/configs/ls2080aqds_nand_defconfig b/configs/ls2080aqds_nand_defconfig index 7d3cce0751..9fc1801c15 100644 --- a/configs/ls2080aqds_nand_defconfig +++ b/configs/ls2080aqds_nand_defconfig @@ -79,6 +79,7 @@ CONFIG_DYNAMIC_DDR_CLK_FREQ=y CONFIG_DIMM_SLOTS_PER_CTLR=2 CONFIG_DDR_ECC=y CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y +CONFIG_SYS_FSL_DDR_INTLV_256B=y CONFIG_SYS_I2C_LEGACY=y CONFIG_SYS_I2C_EARLY_INIT=y CONFIG_SYS_I2C_EEPROM_ADDR=0x57 diff --git a/configs/ls2080aqds_qspi_defconfig b/configs/ls2080aqds_qspi_defconfig index 6bb37819c1..d2dd95ea79 100644 --- a/configs/ls2080aqds_qspi_defconfig +++ b/configs/ls2080aqds_qspi_defconfig @@ -60,6 +60,7 @@ CONFIG_DYNAMIC_DDR_CLK_FREQ=y CONFIG_DIMM_SLOTS_PER_CTLR=2 CONFIG_DDR_ECC=y CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y +CONFIG_SYS_FSL_DDR_INTLV_256B=y CONFIG_SYS_I2C_LEGACY=y CONFIG_SYS_I2C_EARLY_INIT=y CONFIG_SYS_I2C_EEPROM_ADDR=0x57 diff --git a/configs/ls2080aqds_sdcard_defconfig b/configs/ls2080aqds_sdcard_defconfig index e2710b8ec7..e2e4cfdd93 100644 --- a/configs/ls2080aqds_sdcard_defconfig +++ b/configs/ls2080aqds_sdcard_defconfig @@ -74,6 +74,7 @@ CONFIG_DYNAMIC_DDR_CLK_FREQ=y CONFIG_DIMM_SLOTS_PER_CTLR=2 CONFIG_DDR_ECC=y CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y +CONFIG_SYS_FSL_DDR_INTLV_256B=y CONFIG_SYS_I2C_LEGACY=y CONFIG_SYS_I2C_EARLY_INIT=y CONFIG_SYS_I2C_EEPROM_ADDR=0x57 diff --git a/configs/ls2080ardb_SECURE_BOOT_defconfig b/configs/ls2080ardb_SECURE_BOOT_defconfig index 1d0aea08b4..5378876f11 100644 --- a/configs/ls2080ardb_SECURE_BOOT_defconfig +++ b/configs/ls2080ardb_SECURE_BOOT_defconfig @@ -60,6 +60,7 @@ CONFIG_DDR_CLK_FREQ=133333333 CONFIG_DIMM_SLOTS_PER_CTLR=2 CONFIG_DDR_ECC=y CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y +CONFIG_SYS_FSL_DDR_INTLV_256B=y CONFIG_SYS_I2C_LEGACY=y CONFIG_SYS_I2C_EEPROM_ADDR=0x57 CONFIG_FSL_ESDHC=y diff --git a/configs/ls2080ardb_defconfig b/configs/ls2080ardb_defconfig index ec6869cf54..6570a466e0 100644 --- a/configs/ls2080ardb_defconfig +++ b/configs/ls2080ardb_defconfig @@ -63,6 +63,7 @@ CONFIG_DDR_CLK_FREQ=133333333 CONFIG_DIMM_SLOTS_PER_CTLR=2 CONFIG_DDR_ECC=y CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y +CONFIG_SYS_FSL_DDR_INTLV_256B=y CONFIG_SYS_I2C_LEGACY=y CONFIG_SYS_I2C_EEPROM_ADDR=0x57 CONFIG_FSL_ESDHC=y diff --git a/configs/ls2080ardb_nand_defconfig b/configs/ls2080ardb_nand_defconfig index fa929ac4da..7c87f890c2 100644 --- a/configs/ls2080ardb_nand_defconfig +++ b/configs/ls2080ardb_nand_defconfig @@ -83,6 +83,7 @@ CONFIG_DDR_CLK_FREQ=133333333 CONFIG_DIMM_SLOTS_PER_CTLR=2 CONFIG_DDR_ECC=y CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y +CONFIG_SYS_FSL_DDR_INTLV_256B=y CONFIG_SYS_I2C_LEGACY=y CONFIG_SYS_I2C_EEPROM_ADDR=0x57 CONFIG_FSL_ESDHC=y diff --git a/configs/ls2081ardb_defconfig b/configs/ls2081ardb_defconfig index e6e6fe6efc..a426d6d48f 100644 --- a/configs/ls2081ardb_defconfig +++ b/configs/ls2081ardb_defconfig @@ -61,6 +61,7 @@ CONFIG_DDR_CLK_FREQ=133333333 CONFIG_DIMM_SLOTS_PER_CTLR=2 CONFIG_DDR_ECC=y CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y +CONFIG_SYS_FSL_DDR_INTLV_256B=y CONFIG_SYS_I2C_LEGACY=y CONFIG_SYS_I2C_EARLY_INIT=y CONFIG_SYS_I2C_EEPROM_ADDR=0x57 diff --git a/configs/ls2088aqds_tfa_defconfig b/configs/ls2088aqds_tfa_defconfig index 2a7cbd3a1b..f082fa52bc 100644 --- a/configs/ls2088aqds_tfa_defconfig +++ b/configs/ls2088aqds_tfa_defconfig @@ -66,6 +66,7 @@ CONFIG_DYNAMIC_DDR_CLK_FREQ=y CONFIG_DIMM_SLOTS_PER_CTLR=2 CONFIG_DDR_ECC=y CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y +CONFIG_SYS_FSL_DDR_INTLV_256B=y CONFIG_MPC8XXX_GPIO=y CONFIG_DM_I2C=y CONFIG_I2C_SET_DEFAULT_BUS_NUM=y diff --git a/configs/ls2088ardb_qspi_SECURE_BOOT_defconfig b/configs/ls2088ardb_qspi_SECURE_BOOT_defconfig index 5d9c48b139..1972fc908f 100644 --- a/configs/ls2088ardb_qspi_SECURE_BOOT_defconfig +++ b/configs/ls2088ardb_qspi_SECURE_BOOT_defconfig @@ -56,6 +56,7 @@ CONFIG_DDR_CLK_FREQ=133333333 CONFIG_DIMM_SLOTS_PER_CTLR=2 CONFIG_DDR_ECC=y CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y +CONFIG_SYS_FSL_DDR_INTLV_256B=y CONFIG_MPC8XXX_GPIO=y CONFIG_SYS_I2C_LEGACY=y CONFIG_SYS_I2C_EARLY_INIT=y diff --git a/configs/ls2088ardb_qspi_defconfig b/configs/ls2088ardb_qspi_defconfig index 0628cc274d..dedc191edc 100644 --- a/configs/ls2088ardb_qspi_defconfig +++ b/configs/ls2088ardb_qspi_defconfig @@ -63,6 +63,7 @@ CONFIG_DDR_CLK_FREQ=133333333 CONFIG_DIMM_SLOTS_PER_CTLR=2 CONFIG_DDR_ECC=y CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y +CONFIG_SYS_FSL_DDR_INTLV_256B=y CONFIG_MPC8XXX_GPIO=y CONFIG_SYS_I2C_LEGACY=y CONFIG_SYS_I2C_EARLY_INIT=y diff --git a/configs/ls2088ardb_tfa_SECURE_BOOT_defconfig b/configs/ls2088ardb_tfa_SECURE_BOOT_defconfig index 5fb1346054..1674a2ce09 100644 --- a/configs/ls2088ardb_tfa_SECURE_BOOT_defconfig +++ b/configs/ls2088ardb_tfa_SECURE_BOOT_defconfig @@ -61,6 +61,7 @@ CONFIG_DDR_CLK_FREQ=133333333 CONFIG_DIMM_SLOTS_PER_CTLR=2 CONFIG_DDR_ECC=y CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y +CONFIG_SYS_FSL_DDR_INTLV_256B=y CONFIG_MPC8XXX_GPIO=y CONFIG_DM_I2C=y CONFIG_I2C_SET_DEFAULT_BUS_NUM=y diff --git a/configs/ls2088ardb_tfa_defconfig b/configs/ls2088ardb_tfa_defconfig index bf9a016c7e..071db6b1d2 100644 --- a/configs/ls2088ardb_tfa_defconfig +++ b/configs/ls2088ardb_tfa_defconfig @@ -68,6 +68,7 @@ CONFIG_DDR_CLK_FREQ=133333333 CONFIG_DIMM_SLOTS_PER_CTLR=2 CONFIG_DDR_ECC=y CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y +CONFIG_SYS_FSL_DDR_INTLV_256B=y CONFIG_MPC8XXX_GPIO=y CONFIG_DM_I2C=y CONFIG_I2C_SET_DEFAULT_BUS_NUM=y diff --git a/configs/lx2160aqds_tfa_SECURE_BOOT_defconfig b/configs/lx2160aqds_tfa_SECURE_BOOT_defconfig index 21c60524f4..84aea7fb17 100644 --- a/configs/lx2160aqds_tfa_SECURE_BOOT_defconfig +++ b/configs/lx2160aqds_tfa_SECURE_BOOT_defconfig @@ -61,6 +61,7 @@ CONFIG_DYNAMIC_DDR_CLK_FREQ=y CONFIG_DIMM_SLOTS_PER_CTLR=2 CONFIG_DDR_ECC=y CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y +CONFIG_SYS_FSL_DDR_INTLV_256B=y CONFIG_MPC8XXX_GPIO=y CONFIG_DM_I2C=y CONFIG_I2C_SET_DEFAULT_BUS_NUM=y diff --git a/configs/lx2160aqds_tfa_defconfig b/configs/lx2160aqds_tfa_defconfig index 62b214bc0b..7fce30b331 100644 --- a/configs/lx2160aqds_tfa_defconfig +++ b/configs/lx2160aqds_tfa_defconfig @@ -68,6 +68,7 @@ CONFIG_DYNAMIC_DDR_CLK_FREQ=y CONFIG_DIMM_SLOTS_PER_CTLR=2 CONFIG_DDR_ECC=y CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y +CONFIG_SYS_FSL_DDR_INTLV_256B=y CONFIG_MPC8XXX_GPIO=y CONFIG_DM_I2C=y CONFIG_I2C_SET_DEFAULT_BUS_NUM=y diff --git a/configs/lx2160ardb_tfa_SECURE_BOOT_defconfig b/configs/lx2160ardb_tfa_SECURE_BOOT_defconfig index 65e43bf746..42efefa416 100644 --- a/configs/lx2160ardb_tfa_SECURE_BOOT_defconfig +++ b/configs/lx2160ardb_tfa_SECURE_BOOT_defconfig @@ -59,6 +59,7 @@ CONFIG_DYNAMIC_DDR_CLK_FREQ=y CONFIG_DIMM_SLOTS_PER_CTLR=2 CONFIG_DDR_ECC=y CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y +CONFIG_SYS_FSL_DDR_INTLV_256B=y CONFIG_MPC8XXX_GPIO=y CONFIG_DM_I2C=y CONFIG_I2C_SET_DEFAULT_BUS_NUM=y diff --git a/configs/lx2160ardb_tfa_defconfig b/configs/lx2160ardb_tfa_defconfig index 8cdebc808e..85ee4ca845 100644 --- a/configs/lx2160ardb_tfa_defconfig +++ b/configs/lx2160ardb_tfa_defconfig @@ -67,6 +67,7 @@ CONFIG_DYNAMIC_DDR_CLK_FREQ=y CONFIG_DIMM_SLOTS_PER_CTLR=2 CONFIG_DDR_ECC=y CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y +CONFIG_SYS_FSL_DDR_INTLV_256B=y CONFIG_MPC8XXX_GPIO=y CONFIG_DM_I2C=y CONFIG_I2C_SET_DEFAULT_BUS_NUM=y diff --git a/configs/lx2160ardb_tfa_stmm_defconfig b/configs/lx2160ardb_tfa_stmm_defconfig index c7e9afe0a2..547c8682e5 100644 --- a/configs/lx2160ardb_tfa_stmm_defconfig +++ b/configs/lx2160ardb_tfa_stmm_defconfig @@ -67,6 +67,7 @@ CONFIG_DYNAMIC_DDR_CLK_FREQ=y CONFIG_DIMM_SLOTS_PER_CTLR=2 CONFIG_DDR_ECC=y CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y +CONFIG_SYS_FSL_DDR_INTLV_256B=y CONFIG_MPC8XXX_GPIO=y CONFIG_DM_I2C=y CONFIG_I2C_SET_DEFAULT_BUS_NUM=y diff --git a/configs/lx2162aqds_tfa_SECURE_BOOT_defconfig b/configs/lx2162aqds_tfa_SECURE_BOOT_defconfig index ca70f8b5cc..421008489b 100644 --- a/configs/lx2162aqds_tfa_SECURE_BOOT_defconfig +++ b/configs/lx2162aqds_tfa_SECURE_BOOT_defconfig @@ -63,6 +63,7 @@ CONFIG_DYNAMIC_DDR_CLK_FREQ=y CONFIG_DIMM_SLOTS_PER_CTLR=2 CONFIG_DDR_ECC=y CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y +CONFIG_SYS_FSL_DDR_INTLV_256B=y CONFIG_MPC8XXX_GPIO=y CONFIG_DM_I2C=y CONFIG_I2C_SET_DEFAULT_BUS_NUM=y diff --git a/configs/lx2162aqds_tfa_defconfig b/configs/lx2162aqds_tfa_defconfig index 68cdefb52e..dd1c076098 100644 --- a/configs/lx2162aqds_tfa_defconfig +++ b/configs/lx2162aqds_tfa_defconfig @@ -70,6 +70,7 @@ CONFIG_DYNAMIC_DDR_CLK_FREQ=y CONFIG_DIMM_SLOTS_PER_CTLR=2 CONFIG_DDR_ECC=y CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y +CONFIG_SYS_FSL_DDR_INTLV_256B=y CONFIG_MPC8XXX_GPIO=y CONFIG_DM_I2C=y CONFIG_I2C_SET_DEFAULT_BUS_NUM=y diff --git a/configs/lx2162aqds_tfa_verified_boot_defconfig b/configs/lx2162aqds_tfa_verified_boot_defconfig index ee3134e80c..70faef8372 100644 --- a/configs/lx2162aqds_tfa_verified_boot_defconfig +++ b/configs/lx2162aqds_tfa_verified_boot_defconfig @@ -71,6 +71,7 @@ CONFIG_DYNAMIC_DDR_CLK_FREQ=y CONFIG_DIMM_SLOTS_PER_CTLR=2 CONFIG_DDR_ECC=y CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y +CONFIG_SYS_FSL_DDR_INTLV_256B=y CONFIG_MPC8XXX_GPIO=y CONFIG_DM_I2C=y CONFIG_I2C_SET_DEFAULT_BUS_NUM=y diff --git a/drivers/ddr/fsl/Kconfig b/drivers/ddr/fsl/Kconfig index d93ed8d2fe..22400a9b8b 100644 --- a/drivers/ddr/fsl/Kconfig +++ b/drivers/ddr/fsl/Kconfig @@ -182,6 +182,13 @@ config SYS_DDR_RAW_TIMING timing parameters are extracted from datasheet and hard-coded into header files or board specific files. +config SYS_FSL_DDR_INTLV_256B + bool "Enforce 256-byte interleave" + help + DDR controller interleaving on 256-byte. This is a special + interleaving mode, handled by Dickens for Freescale layerscape SoCs + with ARM core. + endif menu "PowerPC / M68K initial memory controller definitions (FLASH, SDRAM, etc)" diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h index 3e86d1bff2..ba5af6c34d 100644 --- a/include/configs/ls2080a_common.h +++ b/include/configs/ls2080a_common.h @@ -16,8 +16,6 @@ /* Link Definitions */ -#define CONFIG_SYS_FSL_DDR_INTLV_256B /* force 256 byte interleaving */ - #define CONFIG_VERY_BIG_RAM #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 diff --git a/include/configs/lx2160a_common.h b/include/configs/lx2160a_common.h index 0f5b0444e7..61870717e8 100644 --- a/include/configs/lx2160a_common.h +++ b/include/configs/lx2160a_common.h @@ -13,7 +13,6 @@ #define CONFIG_SYS_FLASH_BASE 0x20000000 /* DDR */ -#define CONFIG_SYS_FSL_DDR_INTLV_256B /* force 256 byte interleaving */ #define CONFIG_VERY_BIG_RAM #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 |