diff options
| author | Eugeniy Paltsev <eugeniy.paltsev@synopsys.com> | 2019-02-25 18:35:29 +0300 |
|---|---|---|
| committer | Alexey Brodkin <abrodkin@synopsys.com> | 2019-04-18 09:12:38 +0300 |
| commit | 54858311df4f4268b079dff9320f14c91e50dd8e (patch) | |
| tree | 70a7083246c5a78876dee5aea9e94e2f23338e22 | |
| parent | 15736e288e0654a2c58be4b34e5502d18c9b529c (diff) | |
ARC: [plat-hsdk]: migrate to DM_MMC
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
| -rw-r--r-- | arch/arc/dts/hsdk.dts | 26 | ||||
| -rw-r--r-- | board/synopsys/hsdk/hsdk.c | 41 | ||||
| -rw-r--r-- | configs/hsdk_defconfig | 2 |
3 files changed, 34 insertions, 35 deletions
diff --git a/arch/arc/dts/hsdk.dts b/arch/arc/dts/hsdk.dts index 5e9ba054a4..7028050447 100644 --- a/arch/arc/dts/hsdk.dts +++ b/arch/arc/dts/hsdk.dts @@ -86,6 +86,32 @@ reg = <0xf0060000 0x100>; }; + mmcclk_ciu: mmcclk-ciu { + compatible = "fixed-clock"; + /* + * DW sdio controller has external ciu clock divider + * controlled via register in SDIO IP. Due to its + * unexpected default value (it should divide by 1 + * but it divides by 8) SDIO IP uses wrong clock and + * works unstable (see STAR 9001204800) + * We switched to the minimum possible value of the + * divisor (div-by-2) in HSDK platform code. + * So default mmcclk ciu clock is 50000000 Hz. + */ + clock-frequency = <50000000>; + #clock-cells = <0>; + }; + + mmc: mmc0@f000a000 { + compatible = "snps,dw-mshc"; + reg = <0xf000a000 0x400>; + bus-width = <4>; + fifo-depth = <256>; + clocks = <&cgu_clk CLK_SYS_SDIO>, <&mmcclk_ciu>; + clock-names = "biu", "ciu"; + max-frequency = <25000000>; + }; + spi0: spi@f0020000 { compatible = "snps,dw-apb-ssi"; reg = <0xf0020000 0x1000>; diff --git a/board/synopsys/hsdk/hsdk.c b/board/synopsys/hsdk/hsdk.c index 8a2c201477..ac4d980c49 100644 --- a/board/synopsys/hsdk/hsdk.c +++ b/board/synopsys/hsdk/hsdk.c @@ -982,6 +982,12 @@ int board_early_init_f(void) */ init_memory_bridge(); + /* + * Switch SDIO external ciu clock divider from default div-by-8 to + * minimum possible div-by-2. + */ + writel(SDIO_UHS_REG_EXT_DIV_2, (void __iomem *)SDIO_UHS_REG_EXT); + return 0; } @@ -1019,41 +1025,6 @@ int board_late_init(void) return 0; } -int board_mmc_getcd(struct mmc *mmc) -{ - struct dwmci_host *host = mmc->priv; - - return !(dwmci_readl(host, DWMCI_CDETECT) & 1); -} - -int board_mmc_init(bd_t *bis) -{ - struct dwmci_host *host = NULL; - - host = malloc(sizeof(struct dwmci_host)); - if (!host) { - printf("dwmci_host malloc fail!\n"); - return 1; - } - - /* - * Switch SDIO external ciu clock divider from default div-by-8 to - * minimum possible div-by-2. - */ - writel(SDIO_UHS_REG_EXT_DIV_2, (void __iomem *)SDIO_UHS_REG_EXT); - - memset(host, 0, sizeof(struct dwmci_host)); - host->name = "Synopsys Mobile storage"; - host->ioaddr = (void *)ARC_DWMMC_BASE; - host->buswidth = 4; - host->dev_index = 0; - host->bus_hz = 50000000; - - add_dwmci(host, host->bus_hz / 2, 400000); - - return 0; -} - int checkboard(void) { puts("Board: Synopsys ARC HS Development Kit\n"); diff --git a/configs/hsdk_defconfig b/configs/hsdk_defconfig index e0eb6bdb34..e28ceae289 100644 --- a/configs/hsdk_defconfig +++ b/configs/hsdk_defconfig @@ -38,7 +38,9 @@ CONFIG_CLK_HSDK=y CONFIG_DM_GPIO=y CONFIG_HSDK_CREG_GPIO=y CONFIG_MMC=y +CONFIG_DM_MMC=y CONFIG_MMC_DW=y +CONFIG_MMC_DW_SNPS=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_SST=y |