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authorPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>2015-06-18 00:39:41 +0200
committerKlaus Goger <klaus.goger@theobroma-systems.com>2015-07-30 18:44:05 +0200
commit617a6ea60b3d483bf2d151082bc34cc88d77a742 (patch)
treef19fa2656f64d4646061e9453649741471cbf6be
parent7e5a710791859e55c080dffbdedb1a1485daf8c7 (diff)
[fix/squash] remove duplicate setting of CCM_PLL5_CTRL_UPD
-rw-r--r--arch/arm/cpu/armv7/sunxi/clock_sun6i.c2
1 files changed, 0 insertions, 2 deletions
diff --git a/arch/arm/cpu/armv7/sunxi/clock_sun6i.c b/arch/arm/cpu/armv7/sunxi/clock_sun6i.c
index 986c4905fa..709178bf17 100644
--- a/arch/arm/cpu/armv7/sunxi/clock_sun6i.c
+++ b/arch/arm/cpu/armv7/sunxi/clock_sun6i.c
@@ -192,8 +192,6 @@ void clock_set_pll5(unsigned int clk, bool sigma_delta_enable)
CCM_PLL5_CTRL_N(clk / (24000000 * k / m)) |
CCM_PLL5_CTRL_K(k) | CCM_PLL5_CTRL_M(m), &ccm->pll5_cfg);
- setbits_le32(&ccm->pll5_cfg, CCM_PLL5_CTRL_UPD);
-
/* On PLL5, the update needs first to take effect (i.e. CCM_PLL5_CTRL_UPD
* must auto-clear... and only then we can wait for the PLL to lock. */
while (readl(&ccm->pll5_cfg) & CCM_PLL5_CTRL_UPD)