1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
|
// SPDX-License-Identifier: BSD-2-Clause
/*
* Copyright (c) 2016, Linaro Limited
*/
#include <assert.h>
#include <kernel/dt.h>
#include <kernel/linker.h>
#include <libfdt.h>
#include <mm/core_memprot.h>
#include <mm/core_mmu.h>
#include <string.h>
#include <trace.h>
const struct dt_driver *dt_find_compatible_driver(const void *fdt, int offs)
{
const struct dt_device_match *dm;
const struct dt_driver *drv;
for_each_dt_driver(drv) {
for (dm = drv->match_table; dm; dm++) {
if (!dm->compatible) {
break;
}
if (!fdt_node_check_compatible(fdt, offs,
dm->compatible)) {
return drv;
}
}
}
return NULL;
}
const struct dt_driver *__dt_driver_start(void)
{
return &__rodata_dtdrv_start;
}
const struct dt_driver *__dt_driver_end(void)
{
return &__rodata_dtdrv_end;
}
bool dt_have_prop(const void *fdt, int offs, const char *propname)
{
const void *prop;
prop = fdt_getprop(fdt, offs, propname, NULL);
return prop;
}
int dt_map_dev(const void *fdt, int offs, vaddr_t *base, size_t *size)
{
enum teecore_memtypes mtype;
paddr_t pbase;
vaddr_t vbase;
ssize_t sz;
int st;
assert(cpu_mmu_enabled());
st = _fdt_get_status(fdt, offs);
if (st == DT_STATUS_DISABLED)
return -1;
pbase = _fdt_reg_base_address(fdt, offs);
if (pbase == DT_INFO_INVALID_REG)
return -1;
sz = _fdt_reg_size(fdt, offs);
if (sz < 0)
return -1;
if ((st & DT_STATUS_OK_SEC) && !(st & DT_STATUS_OK_NSEC))
mtype = MEM_AREA_IO_SEC;
else
mtype = MEM_AREA_IO_NSEC;
/* Check if we have a mapping, create one if needed */
if (!core_mmu_add_mapping(mtype, pbase, sz)) {
EMSG("Failed to map %zu bytes at PA 0x%"PRIxPA,
(size_t)sz, pbase);
return -1;
}
vbase = (vaddr_t)phys_to_virt(pbase, mtype);
if (!vbase) {
EMSG("Failed to get VA for PA 0x%"PRIxPA, pbase);
return -1;
}
*base = vbase;
*size = sz;
return 0;
}
/* Read a physical address (n=1 or 2 cells) */
static paddr_t _fdt_read_paddr(const uint32_t *cell, int n)
{
paddr_t addr;
if (n < 1 || n > 2)
goto bad;
addr = fdt32_to_cpu(*cell);
cell++;
if (n == 2) {
#ifdef ARM32
if (addr) {
/* High order 32 bits can't be nonzero */
goto bad;
}
addr = fdt32_to_cpu(*cell);
#else
addr = (addr << 32) | fdt32_to_cpu(*cell);
#endif
}
if (!addr)
goto bad;
return addr;
bad:
return DT_INFO_INVALID_REG;
}
paddr_t _fdt_reg_base_address(const void *fdt, int offs)
{
const void *reg;
int ncells;
int len;
int parent;
parent = fdt_parent_offset(fdt, offs);
if (parent < 0)
return DT_INFO_INVALID_REG;
reg = fdt_getprop(fdt, offs, "reg", &len);
if (!reg)
return DT_INFO_INVALID_REG;
ncells = fdt_address_cells(fdt, parent);
if (ncells < 0)
return DT_INFO_INVALID_REG;
return _fdt_read_paddr(reg, ncells);
}
ssize_t _fdt_reg_size(const void *fdt, int offs)
{
const uint32_t *reg;
uint32_t sz;
int n;
int len;
int parent;
parent = fdt_parent_offset(fdt, offs);
if (parent < 0)
return DT_INFO_INVALID_REG;
reg = (const uint32_t *)fdt_getprop(fdt, offs, "reg", &len);
if (!reg)
return -1;
n = fdt_address_cells(fdt, parent);
if (n < 1 || n > 2)
return -1;
reg += n;
n = fdt_size_cells(fdt, parent);
if (n < 1 || n > 2)
return -1;
sz = fdt32_to_cpu(*reg);
if (n == 2) {
if (sz)
return -1;
reg++;
sz = fdt32_to_cpu(*reg);
}
return sz;
}
static bool is_okay(const char *st, int len)
{
return !strncmp(st, "ok", len) || !strncmp(st, "okay", len);
}
int _fdt_get_status(const void *fdt, int offs)
{
const char *prop;
int st = 0;
int len;
prop = fdt_getprop(fdt, offs, "status", &len);
if (!prop || is_okay(prop, len)) {
/* If status is not specified, it defaults to "okay" */
st |= DT_STATUS_OK_NSEC;
}
prop = fdt_getprop(fdt, offs, "secure-status", &len);
if (!prop) {
/*
* When secure-status is not specified it defaults to the same
* value as status
*/
if (st & DT_STATUS_OK_NSEC)
st |= DT_STATUS_OK_SEC;
} else {
if (is_okay(prop, len))
st |= DT_STATUS_OK_SEC;
}
return st;
}
void _fdt_fill_device_info(void *fdt, struct dt_node_info *info, int offs)
{
struct dt_node_info dinfo = {
.reg = DT_INFO_INVALID_REG,
.clock = DT_INFO_INVALID_CLOCK,
.reset = DT_INFO_INVALID_RESET,
};
const fdt32_t *cuint;
dinfo.reg = _fdt_reg_base_address(fdt, offs);
cuint = fdt_getprop(fdt, offs, "clocks", NULL);
if (cuint) {
cuint++;
dinfo.clock = (int)fdt32_to_cpu(*cuint);
}
cuint = fdt_getprop(fdt, offs, "resets", NULL);
if (cuint) {
cuint++;
dinfo.reset = (int)fdt32_to_cpu(*cuint);
}
dinfo.status = _fdt_get_status(fdt, offs);
*info = dinfo;
}
|
