blob: a5e92244e441c572d1338dc27677c754d6f28520 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
|
/* SPDX-License-Identifier: BSD-2-Clause */
/*
* Copyright (c) 2015, Linaro Limited
* All rights reserved.
*/
#ifndef PLATFORM_CONFIG_H
#define PLATFORM_CONFIG_H
#define DRAM0_BASE 0x80000000
#define DRAM0_SIZE 0x80000000
#if defined(PLATFORM_FLAVOR_dra7xx) || defined(PLATFORM_FLAVOR_am57xx)
/* Location of protected DDR on the DRA7xx platform */
#define TZDRAM_BASE 0xbdb00000
#define TZDRAM_SIZE 0x01c00000
#ifdef CFG_WITH_PAGER
#define TZSRAM_BASE 0x40300000
#define TZSRAM_SIZE (256 * 1024)
#endif /* CFG_WITH_PAGER */
#define CFG_TEE_CORE_NB_CORE 2
#define UART1_BASE 0x4806A000
#define UART2_BASE 0x4806C000
#define UART3_BASE 0x48020000
#if defined(PLATFORM_FLAVOR_dra7xx)
#define CONSOLE_UART_BASE UART1_BASE
#elif defined(PLATFORM_FLAVOR_am57xx)
#define CONSOLE_UART_BASE UART3_BASE
#else
#error "Unknown platform flavor"
#endif
#define CONSOLE_BAUDRATE 115200
#define CONSOLE_UART_CLK_IN_HZ 48000000
#define SCU_BASE 0x48210000
#define GICC_OFFSET 0x2000
#define GICC_SIZE 0x1000
#define GICD_OFFSET 0x1000
#define GICD_SIZE 0x1000
#define GICC_BASE (SCU_BASE + GICC_OFFSET)
#define GICD_BASE (SCU_BASE + GICD_OFFSET)
#define SECRAM_BASE 0x40200000
#define SECRAM_SIZE 0x00100000
/* RNG */
#define RNG_BASE 0x48090000
#elif defined(PLATFORM_FLAVOR_am43xx)
/* Location of protected DDR on the AM43xx platform */
#define TZDRAM_BASE 0xbdb00000
#define TZDRAM_SIZE 0x01c00000
#define CFG_TEE_CORE_NB_CORE 1
#define UART0_BASE 0x44E09000
#define UART1_BASE 0x48022000
#define UART2_BASE 0x48024000
#define UART3_BASE 0x481A6000
#define UART4_BASE 0x481A8000
#define UART5_BASE 0x481AA000
#define CONSOLE_UART_BASE UART0_BASE
#define CONSOLE_BAUDRATE 115200
#define CONSOLE_UART_CLK_IN_HZ 48000000
#define SCU_BASE 0x48240000
#define GICD_OFFSET 0x1000
#define GICD_SIZE 0x1000
#define GICC_OFFSET 0x0100
#define GICC_SIZE 0x0100
#define PL310_OFFSET 0x2000
#define PL310_SIZE 0x1000
#define GICD_BASE (SCU_BASE + GICD_OFFSET)
#define GICC_BASE (SCU_BASE + GICC_OFFSET)
#define PL310_BASE (SCU_BASE + PL310_OFFSET)
#define SECRAM_BASE 0x402F0000
#define SECRAM_SIZE 0x00100000
/* RNG */
#define RNG_BASE 0x48310000
#else
#error "Unknown platform flavor"
#endif
/* Make stacks aligned to data cache line length */
#define STACK_ALIGNMENT 64
#ifdef CFG_WITH_PAGER
/*
* Use TZSRAM for TEE, page out everything else to TZDRAM.
* +--------+----------+
* | DRAM | SHMEM |
* +--------+----------+
* | | TA_RAM |
* | TZDRAM +----------+
* | | PAGE_RAM |
* +--------+----------+
* | TZSRAM | TEE_RAM |
* +--------+----------+
*/
#define CFG_TEE_RAM_VA_SIZE (1 * 1024 * 1024)
#define CFG_TEE_RAM_PH_SIZE TZSRAM_SIZE
#define CFG_TEE_RAM_START TZSRAM_BASE
#define CFG_TEE_LOAD_ADDR (CFG_TEE_RAM_START + 0x1000)
#else /* CFG_WITH_PAGER */
/*
* Assumes that either TZSRAM isn't large enough or TZSRAM doesn't exist,
* everything is in TZDRAM.
* +--------+---------+
* | DRAM | SHMEM |
* +--------+---------+
* | | TA_RAM |
* | TZDRAM +---------+
* | | TEE_RAM |
* +--------+---------+
*/
#define CFG_TEE_RAM_VA_SIZE (1 * 1024 * 1024)
#define CFG_TEE_RAM_PH_SIZE CFG_TEE_RAM_VA_SIZE
#define CFG_TEE_RAM_START TZDRAM_BASE
#define CFG_TEE_LOAD_ADDR CFG_TEE_RAM_START
#endif /* CFG_WITH_PAGER */
#if defined(CFG_SECURE_DATA_PATH)
/* Locate SDP memory at the end of TZDRAM */
#define CFG_TEE_SDP_MEM_BASE (TZDRAM_BASE + \
TZDRAM_SIZE - \
CFG_TEE_SDP_MEM_SIZE)
#endif
#define CFG_TA_RAM_START ROUNDUP((TZDRAM_BASE + CFG_TEE_RAM_VA_SIZE), \
CORE_MMU_DEVICE_SIZE)
#define CFG_TA_RAM_SIZE ROUNDDOWN((TZDRAM_SIZE - CFG_TEE_RAM_VA_SIZE) - \
CFG_TEE_SDP_MEM_SIZE, \
CORE_MMU_DEVICE_SIZE)
/* Full GlobalPlatform test suite requires CFG_SHMEM_SIZE to be at least 2MB */
#define CFG_SHMEM_START (TZDRAM_BASE + TZDRAM_SIZE)
#define CFG_SHMEM_SIZE (4 * 1024 * 1024)
#endif /*PLATFORM_CONFIG_H*/
|
