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2019-02-14sunxi: upgrade from write32() to io_write32() and friendsEtienne Carriere
Replace use of readX() and writeX() with io_readX() and io_writeX(). The former are about to be deprecated in favor to the later. Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org> Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
2019-02-13core_mmu: do not restrict device memory mapping to PGDIR_SIZE granularityJerome Forissier
Device memory registered via register_phys_mem() is currently rounded up/down to CORE_MMU_PGDIR_SIZE (1 MiB, or 2 MiB for LPAE). This is not needed and possibly incorrect for SoCs that define I/O memory maps with regions aligned on a small page (4 KiB), because using a larger granularity could result in overlaps between secure and non-secure mappings. This could cause issues depending on the type of memory firewall used by the SoC and its configuration. In any case, memory types other than MEM_AREA_IO_{SEC,NSEC} *can* be mapped with small page granularity using register_phys_mem(), so the situation is a bit inconsistent. This commit removes the rounding by default and provides a new macro: register_phys_mem_pgdir(). Platforms that still need to use PGDIR_SIZE granularity (typically because it consumes less page table space) need to replace register_phys_mem() by register_phys_mem_pgdir(). In order to avoid any functional change in platform code, all calls to register_phys_mem() with device memory are replaced with register_phys_mem_pgdir(). In addition, CORE_MMU_DEVICE_SIZE is removed and replaced with CORE_MMU_PGDIR_SIZE since there is no unique mapping size for device memory anymore. Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org> Reported-by: Zeng Tao <prime.zeng@hisilicon.com> Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org> Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
2018-12-18Factor out ta-targets from platform configJerome Forissier
Platforms use the same basic pattern again and again: ta-targets = ta_arm32 ifeq ($(CFG_ARM64_core),y) ta-targets += ta_arm64 endif Let's move this pattern to core/arch/arm/arm.mk, make it the default, and cleanup the platform configuration files. Suggested-by: Jens Wiklander <jens.wiklander@linaro.org> Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org> Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org> Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
2018-08-13plat-sunxi: Add Allwinner A64 supportAmit Singh Tomar
This commit adds support for pine64[1] board based on Allwinner's A64 SoC. 1. Build command # make PLATFORM=sunxi-sun50i_a64 2. Pass optee_example_hello_world and xtest. [1]: https://www.pine64.org/ Acked-by: Jerome Forissier <jerome.forissier@linaro.org> Signed-off-by: Amit Singh Tomar <amittomer25@gmail.com>
2018-06-15plat-sunxi: Add plat-sunxiYing-Chun Liu (PaulLiu)
Initial version support for Allwinner H2+ platform. Specific to Banana Pi M2 zero board currently. Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org> Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org> Signed-off-by: Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org>
2018-01-17Remove support for Allwinner A80 platform (plat-sunxi)Jerome Forissier
It has been almost three years since we have heard about plat-sunxi (no new contributions, no patch ack'ed or tested, no feedback at release time). Therefore, remove support for this platform. Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org> CC: Sun Yangbang <sunny@allwinnertech.com> Reviewed-by: Joakim Bech <joakim.bech@linaro.org> Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
2018-01-16plat-sunxi: ACTLR_CA15_ENABLE_INVALIDATE_BTBJens Wiklander
Enables ACTLR_CA15_ENABLE_INVALIDATE_BTB (ACTLR[0]) if compiled with CFG_CORE_WORKAROUND_SPECTRE_BP or CFG_CORE_WORKAROUND_SPECTRE_BP_SEC. Fixes CVE-2017-5715 Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org> Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
2018-01-15core: assert foreign interrupts are masked in get_core_pos()Etienne Carriere
This change modifies get_core_pos() so that calling the routine from C source asserts the foreign interrupts are masked when the function is called, preventing a cpu migration while reading current core position. There is no assertion of foreign interrupt masking for such calls to get_core_pos() from assembly sources. Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org> Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org> Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
2018-01-10Add SPDX license identifiersJerome Forissier
Adds one SPDX-License-Identifier line [1] to each source files that contains license text. Generated by [2]: spdxify.py --add-spdx optee_os/ The scancode tool [3] was used to double check the license matching code in the Python script. All the licenses detected by scancode are either detected by spdxify.py, or have no SPDX identifier, or are false matches. Link: [1] https://spdx.org/licenses/ Link: [2] https://github.com/jforissier/misc/blob/f7b56c8/spdxify.py Link: [3] https://github.com/nexB/scancode-toolkit Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org> Acked-by: Joakim Bech <joakim.bech@linaro.org>
2017-11-24core: arm32: enable NEON with .fpu directive rather than compile flagJerome Forissier
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org> Tested-by: Jerome Forissier <jerome.forissier@linaro.org> (QEMU CFG_WITH_VFP=y) Tested-by: Jerome Forissier <jerome.forissier@linaro.org> (HiKey960 AArch32 {,pager}) Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
2017-08-25Add support for early Trusted ApplicationsJerome Forissier
Early TAs are user-mode Trusted Applications that are embedded at link time in the TEE binary. A special read-only data section is used to store them (.rodata.early_ta). A Python script takes care of converting the TAs into a C source file with the proper linker section attribute. The feature is disabled by default. To enable it, the paths to the TA binaries have to be given in $(EARLY_TA_PATHS). They should be ELF files. Typical build steps: $ make ... CFG_EARLY_TA=y ta_dev_kit # (1) $ # ... build the TAs ... # (2) $ make ... EARLY_TA_PATHS=path/to/<uuid>.stripped.elf # (3) Notes: - Setting CFG_EARLY_TA=y during the first step (1) is not necessary, but it will avoid rebuilding libraries during the third step (3) - CFG_EARLY_TA is automatically enabled when EARLY_TA_PATHS is non-empty in step (3) - Several TAs may be given in $(EARLY_TA_PATHS) (3) Early TAs are given a higher load priority than REE FS TAs, since they should be available even before tee-supplicant is ready. Suggested-by: Zeng Tao <prime.zeng@hisilicon.com> Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org> Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org> Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
2017-06-16plat-sunxi: provide .bss section initialization before usageViktor Signayevskiy
BSS initialization is executed AFTER the initialization of the MMU table (global variable array "static_memory_map[]"), so the table is overwritten. Change this so that BSS initialization executes BEFORE static_memory_map[] is initialized by core_init_mmu_map(). Signed-off-by: Victor Signaevskyi <piligrim2007@meta.ua> Fixes: https://github.com/OP-TEE/optee_os/issues/1607 Fixes: 236601217f7e ("core: remove __early_bss") Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org> [jf: minor edits to the commit message, add Fixes:] Signed-off-by: Jerome Forissier <jeorme.forissier@linaro.org>
2017-06-12core: arm: make alignment check configurableJerome Forissier
We occasionally get reports from people stumbling upon data abort exceptions caused by alignment faults in TAs. The recommended fix is to change the code so that the unaligned access won't occur. But it is sometimes difficult to achieve. Therefore we provide a compile-time option to disable alignment checks. For AArch64 it applies to both SEL1 and SEL0. Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org> Tested-by: Jerome Forissier <jerome.forissier@linaro.org> (HiKey) Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
2017-06-02core_mmu: add non-secure DDR ranges supportVolodymyr Babchuk
This patch adds new macro `register_nsec_ddr` which allows platform code to register non-secure memory ranges. Signed-off-by: Volodymyr Babchuk <vlad.babchuk@gmail.com> Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org> Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
2017-05-30core: sparse fix: tmp_stackJens Wiklander
Fixes the sparse warnings related to tmp_stack. The fix actually remove some instructions from the assembly code initializing the temporary stack pointer. Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org> Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
2017-05-30core: remove __early_bssJerome Forissier
Initialize the .bss section early from assembler before entering C code. As a result, the __early_bss qualifier is not needed anymore. Remove it, as well as the related symbols (__early_bss_start and __early_bss_end). This makes the code simpler hence easier to maintain, at the expense of initialization time, since .bss is cleared before CPU caches are turned on (and doing it later would mean some C function have been called already). Here are some performance numbers measured on HiKey. The "memset" column measures the time it takes to clear .bss in C, without this patch. The "assembly" column reports the time taken by the clear_bss loop in this patch. Timings were performed using CNTPCT. Worst case is a ~1 ms overhead in boot time. memset(): | assembly: ms (bytes) | ms (bytes) --------------+-------------- Aarch64 0.30 (72824) | 0.08 (73528) Aarch32 0.27 (65016) | 1.24 (65408) Aarch32/pager 0.03 (11328) | 0.23 (11736) Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org> Tested-by: Jerome Forissier <jerome.forissier@linaro.org> (QEMU) Tested-by: Jerome Forissier <jerome.forissier@linaro.org> (HiKey 32/64) Tested-by: Jerome Forissier <jerome.forissier@linaro.org> (HiKey/pager) Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
2017-05-29core: factorize cpu supportEtienne Carriere
Create core/arch/arm/cpu/<cpu-name>.mk to store CPU generic configurations settings. Update supported platforms to rely on the generic CPU support. Platform shall still specify whether they support or not the NEON extension. Cortex-A53 and Cortex-A57 are all ARMv8.0 compliant. For ARMv8 core, we will use ARMv8-A architecture minor version configuration files. Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org> Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
2017-05-19core: label the bounds of core flat mapped memoryEtienne Carriere
Define labels to identify the core memory layout. These labels will be later use to define the mapping bounds between executable and writable memories. Update plat-sunxi/kernel.ld.S to match support of generic_boot.c. Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org> Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
2017-04-12core: deprecate DEVICEx_TYPE/_PA_BASE/_SIZEEtienne Carriere
Macros DEVICEx_TYPE, DEVICEx_PA_BASE and DEVICEx__SIZE used to help platform to register their address range mapping requirements. These are now deprecated since platform should use the more flexible register_phys_mem() macro. This change removes all occurrences of DEVICEx_TYPE/_PA_BASE/_SIZE and use the register_phys_mem() instead. Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org> Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
2017-03-17plat-sunxi: remove console.cJerome Forissier
With the simplification of the console/UART code, we're left with only one function in console.c. Move it to main.c. Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org> Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org> Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
2017-03-17core: add common implementation for console_putc() and console_flush()Jerome Forissier
Since most platforms now use the same console_putc() and console_flush(), move them to core/kernel/console.c. Make them __weak so that platforms may still provide their own. The common code expects the platforms to initialize whatever serial device from console_init() and call register_console(). Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org> Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org> Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
2017-03-17drivers: convert sunxi_uart driver to use struct serial_chipJerome Forissier
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org> Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org> Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
2017-03-16core: rename cache_maintenance_l1() into cache_op_inner()Etienne Carriere
Rename cache_maintenance_l1() into cache_op_inner() to prevent confusion as the function targets inner cache and not only level1 cache. Fix return type of cache_op_inner(). Suggested-by: Jerome Forissier <jerome.forissier@linaro.org> Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org> Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org> Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
2017-02-28Rename the secure and non-secure interruptsDavid Wang
Currently, the secure interrupts are named as FIQ and the non-secure interrupts are named as IRQ. In GICv3 mode, the FIQ and IRQ have different definitions. * Secure Group 0 interrupts: Handled by EL3 and triggered by FIQ when running at Secure EL0/1. * Secure Group 1 interrupts: Handled by optee_os and triggered by IRQ when running at Secure EL0/1. * Non-secure Group1 interrupts: Handled by the rich os and triggered by FIQ when running at Secure EL0/1. The "Secure Group 1" interrupts are the "native" interrupts handled by optee_os. They are same as the "secure" interrupts used in optee_os for now. But they are triggered by FIQ in GICv2 mode while by IRQ in GICv3 mode. The "Secure Group 0" and "Non-secure Group1" interrupts are the "foreign" interrupts that will cause the exiting of optee_os. (e.g. switch back to normal world) The "Non-secure Group1" interrupts are same as the "non-secure"interrupts used in optee_os for now. But they are triggered by IRQ in GICv2 mode while by FIQ in GICv3 mode. This patch renames these interrupts to the generic names - "Foreign interrupts" and "Native interrupts". For the support of GICv3 mode in the future, we can redefine the macros of "native interrupt" and "foreign interrupt" to IRQ and FIQ. Signed-off-by: David Wang <david.wang@arm.com> Reviewed-by: Joakim Bech <joakim.bech@linaro.org> Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org> Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org> Tested-by: Etienne Carriere <etienne.carriere@linaro.org> (b2260)
2016-12-27core_mmu_v7: slight refactoring to look like core_mmu_lpaeVolodymyr Babchuk
This patch makes core_mmu_v7.c to look simmilar to core_mmu_lpae.c - ARMv7-specific definitions was moved from core_mmu_defs.h to .c file - core_mmu_defs.h was removed, because it stored definitions only for v7 - core_mmu_alloc_l2() now really allocates l2 pages Signed-off-by: Volodymyr Babchuk <vlad.babchuk@gmail.com> Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
2016-11-23core: redesign secure monitorJens Wiklander
The secure monitor is redesigned to make it easier to register services. Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org> Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
2016-08-19core: add late service_init and driver_initJens Wiklander
Adds service_init_late() for init calls that depends on other services. Adds driver_init_late() for init calls that depends on other drivers. Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org> Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org> Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
2016-08-17Enable static TA and core self tests..Victor Chong
..for all platforms by setting CFG_TEE_CORE_EMBED_INTERNAL_TESTS ?= y in mk/config.mk. Signed-off-by: Victor Chong <victor.chong@linaro.org> Suggested-by: Jerome Forissier <jerome.forissier@linaro.org> Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org> Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
2016-08-09core: remove TEE_ASSERT()Etienne Carriere
TEE_ASSERT() can be confusing regarding assert() as assert() can be disabled through NDEBUG while TEE_ASSERT() can't. Instead one should explicitly implement "if (cond) { panic(); }" This patch removes several inclusions on tee_common_unpg.h as it used to define TEE_ASSERT() that has been removed. Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org> Reviewed-by: Jens Wiklander <jen.wiklander@linaro.org> Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org> Tested-by: Etienne Carriere <etienne.carriere@linaro.org> (QEMU)
2016-08-09assert/panic: fix misuse of assert/panicEtienne Carriere
Currently implementation of macro assert() does not expand to a no-op when NDEBUG is defined. This will be done in a later change. Before that, fix misuses of assert() and TEE_ASSERT(): - Correct misplaced assert() that should panic() whatever NDEBUG. - Correct misplaced TEE_ASSERT() that should simply assert(). Also cleanup many inclusions of "assert.h" and few calls of assert(). Signed-off-by: Jens Wiklander <jen.wiklander@linaro.org> Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org> Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org> Tested-by: Etienne Carriere <etienne.carriere@linaro.org> (QEMU)
2016-07-07Support CFG_TEE_CORE_NB_CORE > 8Jerome Forissier
Remove the stack_tmp_top[] array. Instead, compute the stack top for each CPU in the assembly code: sp = stack_tmp + (cpu_id + 1) * stack_tmp_stride stack_tmp and stack_tmp_stride are exported by thread.c. Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org> Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org> Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
2016-06-15core: non-linear mapping of secure world devicesJens Wiklander
This patch introduces non-linear mapping of secure world devices, that is, physical and virtual address of a device can differ. Reviewed-by: Joakim Bech <joakim.bech@linaro.org> Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
2016-05-18plat-sunxi: translate pa base addr before useJens Wiklander
Translates physical addresses used for register base addresses before use to be able to handle non-linear mapping of addresses. Reviewed-by: Pascal Brand <pascal.brand@linaro.org> Reviewed-by: Joakim Bech <joakim.bech@linaro.org> Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
2016-05-16plat-sunxi: refactor memory configurationJens Wiklander
Refactors memory configuration to use the same memory configuration scheme as all the other platforms. Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org> Reviewed-by: Pascal Brand <pascal.brand@linaro.org> Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
2016-04-29core: add interrupt frameworkJens Wiklander
Adds interrupt frameworks and adjusts gic driver to fit in. Update plat-vexpress and sunxi platforms to initialize gic with slightly modified interface. Reviewed-by: Pascal Brand <pascal.brand@linaro.org> Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (QEMU, FVP) Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
2016-04-01Fix wrong comment syntaxPascal Brand
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org> Reviewed-by: Joakim Bech <joakim.bech@linaro.org> Signed-off-by: Pascal Brand <pascal.brand@st.com>
2016-03-24stm,vexpress: increase shared memory size from 1 to 2 MiBPascal Brand
This is needed to run the latest "generic driver" configuration. When the shared memory pool is 1 MiB, xtest 7633 fails with a TA panic due to memory allocation error. This commit increases the size of the shared memory pool so that the test will pass. Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org> Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org> Signed-off-by: Pascal Brand <pascal.brand@st.com>
2016-03-22CFG_CRYPTO_SIZE_OPTIMIZATION?=y by defaultPascal Brand
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org> Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org> Signed-off-by: Pascal Brand <pascal.brand@st.com>
2016-03-01core: new OPTEE_MSG interfaceJens Wiklander
* Changes to a new OPTEE_MSG interface to work with the generic TEE driver. * Removes TEESMC64_* defines as the TEESMC32_* functions are enhanced to take 64bit values where required in pairs of 32bit registers instead. * Changes open session meta information to be passed in two value parameters instead of one memref. Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org> Tested-by: Jerome Forissier <jerome.forissier@linaro.org> (HiKey) Tested-by: Pascal Brand <pascal.brand@linaro.org> (STM) Reviewed-by: Pascal Brand <pascal.brand@linaro.org> Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (QEMU, FVP) Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
2016-02-19core: remove CFG_MMU_V7_TTBJens Wiklander
Since all platforms are using CFG_MMU_V7_TTB when applicable the config option is redundant. This patch removes CFG_MMU_V7_TTB and makes some related functions static. Reviewed-by: Pascal Brand <pascal.brand@linaro.org> Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
2016-02-10core: stack unwindingJens Wiklander
Adds support for stack unwinding, currently only done for fatal aborts from kernel mode if CFG_CORE_UNWIND = y The ARMv7/Aarch32 implementation uses -funwind-tables to generate frame unwinding information which is quite large. Enabling stack unwinding currently consumes ~8 KiB. The code to parse the frame unwind information is imported from FreeBSD. The Aarch64 implementation takes advantage of the frame pointer and has minimal overhead. The core code to unwind the stack is imported from FreeBSD. Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org> Tested-by: Jerome Forissier <jerome.forissier@linaro.org> (HiKey 32/64) Reviewed-by: Pascal Brand <pascal.brand@linaro.org> Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (QEMU, FVP) Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
2016-02-05core: remove registration of svc and abort handlersJens Wiklander
Removes the possibility to register svc and abort handlers as the same handler is always used. The svc and abort handlers are also so closely tied to thread system that it would be difficult and error prone to use alternative handlers. Reviewed-by: Pascal Brand <pascal.brand@linaro.org> Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (FVP) Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
2016-02-04arm: add TA hard-float supportJens Wiklander
Adds support for hard-float in TAs. Hard-float is enabled by default for all platforms which are capable, currently all. Soft-float is still available if needed. Reviewed-by: Pascal Brand <pascal.brand@linaro.org> Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org> Tested-by: Jerome Forissier <jerome.forissier@linaro.org> (HiKey) Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (QEMU, FVP) Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
2016-02-02core: abort.{c,h} refactoringJens Wiklander
Renames structs, functions and defines to show that they are part of the abort module. Reviewed-by: Pascal Brand <pascal.brand@linaro.org> Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org> Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (QEMU, FVP) Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
2016-01-29get rid of platform_flags.mkJens Wiklander
Tested-by: Jerome Forissier <jerome.forissier@linaro.org> (HiKey) Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org> Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (QEMU, FVP) Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
2015-12-11Generate new TA dev kit for ARM32 platformsVictor Chong
Signed-off-by: Victor Chong <victor.chong@linaro.org> Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org> Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org> Reviewed-by: Pascal Brand <pascal.brand@linaro.org>
2015-12-04alloc: fix mutex usagePascal Brand
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org> Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org> Signed-off-by: Pascal Brand <pascal.brand@st.com>
2015-11-27Make TEE Core TA interaction 64-bit compatibleJens Wiklander
* Updates TA entry * Update ta_head * Updates the syscall interface * Adds functions to make a short pointer (32-bit uref) from a kernel pointer and vice versa Note that this change is not backwards compatible, TAs needs to be recompiled. Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org> Reviewed-by: Joakim Bech <joakim.bech@linaro.org> Reviewed-by: Pascal Brand <pascal.brand@linaro.org>
2015-11-05core: split tee/entry.cJens Wiklander
Split core/arch/arm/tee/entry.c into entry_fast.c and entry_std.c to separate fast call code from standard call code. Fast call code must not be paged, but standard code should be paged if possible. The pager can only handle page faults for active threads. Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org> Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (QEMU) Reviewed-by: Joakim Bech <joakim.bech@linaro.org>
2015-11-03Delete libutil_with_isocJerome Forissier
OP-TEE won't build unless $(libutil_with_isoc) is 'y', so this variable is not needed. Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org> Reviewed-by: Joakim Bech <joakim.bech@linaro.org>
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