diff options
| -rw-r--r-- | .shippable.yml | 2 | ||||
| -rw-r--r-- | MAINTAINERS.md | 1 | ||||
| -rw-r--r-- | README.md | 1 | ||||
| -rw-r--r-- | core/arch/arm/plat-poplar/conf.mk | 36 | ||||
| -rw-r--r-- | core/arch/arm/plat-poplar/hi3798cv200.h | 14 | ||||
| -rw-r--r-- | core/arch/arm/plat-poplar/main.c | 56 | ||||
| -rw-r--r-- | core/arch/arm/plat-poplar/platform_config.h | 151 | ||||
| -rw-r--r-- | core/arch/arm/plat-poplar/sub.mk | 2 |
8 files changed, 263 insertions, 0 deletions
diff --git a/.shippable.yml b/.shippable.yml index e9a9aef2..370a732a 100644 --- a/.shippable.yml +++ b/.shippable.yml @@ -84,6 +84,8 @@ build: - _make PLATFORM=rpi3 CFG_ARM64_core=y - _make PLATFORM=hikey-hikey960 - _make PLATFORM=hikey-hikey960 CFG_ARM64_core=y + - _make PLATFORM=poplar + - _make PLATFORM=poplar CFG_ARM64_core=y - _make PLATFORM=rockchip-rk322x - _make PLATFORM=sam - _make PLATFORM=marvell-armada7k8k diff --git a/MAINTAINERS.md b/MAINTAINERS.md index 017b224d..386da85a 100644 --- a/MAINTAINERS.md +++ b/MAINTAINERS.md @@ -28,6 +28,7 @@ for these platforms. | Marvell Armada 80x0 |`Kevin Peng <kevinp@marvell.com>`| | Marvell Armada 3700 |`Kevin Peng <kevinp@marvell.com>`| | MediaTek MT8173 EVB Board |`Linaro <op-tee@linaro.org>`| +| Poplar Board (HiSilicon Hi3798C V200) |`Linaro <op-tee@linaro.org>`| | QEMU |`Linaro <op-tee@linaro.org>`| | Raspberry Pi3 |`Linaro <op-tee@linaro.org>`| | Renesas RCAR |`Volodymyr Babchuk <vlad.babchuk@gmail.com>`| @@ -69,6 +69,7 @@ The `Maintained` column shows: | [Marvell ARMADA 8K Family](http://www.marvell.com/embedded-processors/armada-80xx/)|`PLATFORM=marvell-armada7k8k`| Yes |  | | [Marvell ARMADA 3700 Family](http://www.marvell.com/embedded-processors/armada-3700/)|`PLATFORM=marvell-armada3700`| Yes |  | | [MediaTek MT8173 EVB Board](https://www.mediatek.com/products/tablets/mt8173)|`PLATFORM=mediatek-mt8173`| No |  | +| [Poplar Board (HiSilicon Hi3798C V200)](https://www.96boards.org/product/poplar)|`PLATFORM=poplar`| Yes |  | | [QEMU](http://wiki.qemu.org/Main_Page) |`PLATFORM=vexpress-qemu_virt`| Yes |  | | [QEMUv8](http://wiki.qemu.org/Main_Page) |`PLATFORM=vexpress-qemu_armv8a`| Yes |  | | [Raspberry Pi 3](https://www.raspberrypi.org/products/raspberry-pi-3-model-b) |`PLATFORM=rpi3`| Yes |  | diff --git a/core/arch/arm/plat-poplar/conf.mk b/core/arch/arm/plat-poplar/conf.mk new file mode 100644 index 00000000..f416c790 --- /dev/null +++ b/core/arch/arm/plat-poplar/conf.mk @@ -0,0 +1,36 @@ +include core/arch/arm/cpu/cortex-armv8-0.mk + +$(call force,CFG_GENERIC_BOOT,y) +$(call force,CFG_PL011,y) +$(call force,CFG_PM_STUBS,y) +$(call force,CFG_SECURE_TIME_SOURCE_CNTPCT,y) +$(call force,CFG_WITH_ARM_TRUSTED_FW,y) + +ta-targets = ta_arm32 + +ifeq ($(CFG_ARM64_core),y) +$(call force,CFG_WITH_LPAE,y) +ta-targets += ta_arm64 +CFG_CORE_TZSRAM_EMUL_SIZE ?= 655360 +else +$(call force,CFG_ARM32_core,y) +CFG_CORE_TZSRAM_EMUL_SIZE ?= 524288 +endif + +CFG_NUM_THREADS ?= 4 +CFG_CRYPTO_WITH_CE ?= y +CFG_WITH_STACK_CANARIES ?= y +# Overrides default in mk/config.mk with 96 kB +CFG_CORE_HEAP_SIZE ?= 98304 + +CFG_PL061 ?= y + +ifeq ($(CFG_PL061),y) +core-platform-cppflags += -DPLAT_PL061_MAX_GPIOS=104 +endif + +CFG_SECURE_DATA_PATH ?= y +CFG_TEE_SDP_MEM_BASE ?= 0x02800000 +CFG_TEE_SDP_MEM_SIZE ?= 0x00400000 + +CFG_DRAM_SIZE_GB ?= 2 diff --git a/core/arch/arm/plat-poplar/hi3798cv200.h b/core/arch/arm/plat-poplar/hi3798cv200.h new file mode 100644 index 00000000..1b6b61ef --- /dev/null +++ b/core/arch/arm/plat-poplar/hi3798cv200.h @@ -0,0 +1,14 @@ +/* + * Copyright (c) 2017, Linaro Limited + * SPDX-License-Identifier: BSD-2-Clause + */ + +#ifndef __HI3798cv200_H__ +#define __HI3798cv200_H__ + +/* PL011 */ +#define PL011_UART0_BASE (0xF8B00000) +#define PL011_BAUDRATE (115200) +#define PL011_UART0_CLK_IN_HZ (75000000) + +#endif /* __HI3798cv200_H__ */ diff --git a/core/arch/arm/plat-poplar/main.c b/core/arch/arm/plat-poplar/main.c new file mode 100644 index 00000000..9e7b444c --- /dev/null +++ b/core/arch/arm/plat-poplar/main.c @@ -0,0 +1,56 @@ +/* + * Copyright (c) 2017, Linaro Limited + * SPDX-License-Identifier: BSD-2-Clause + */ + +#include <console.h> +#include <drivers/pl011.h> +#ifdef CFG_PL061 +#include <drivers/pl061_gpio.h> +#endif +#include <kernel/generic_boot.h> +#include <kernel/panic.h> +#include <kernel/pm_stubs.h> +#include <mm/tee_pager.h> +#include <mm/core_memprot.h> +#include <platform_config.h> +#include <stdint.h> +#include <tee/entry_std.h> +#include <tee/entry_fast.h> + +static void main_fiq(void); + +static const struct thread_handlers handlers = { + .std_smc = tee_entry_std, + .fast_smc = tee_entry_fast, + .nintr = main_fiq, + .cpu_on = cpu_on_handler, + .cpu_off = pm_do_nothing, + .cpu_suspend = pm_do_nothing, + .cpu_resume = pm_do_nothing, + .system_off = pm_do_nothing, + .system_reset = pm_do_nothing, +}; + +static struct pl011_data console_data; + +register_phys_mem(MEM_AREA_IO_NSEC, CONSOLE_UART_BASE, PL011_REG_SIZE); +/* for dynamic shared memory */ +register_nsec_ddr(DRAM0_BASE_NSEC, DRAM0_SIZE_NSEC); + +const struct thread_handlers *generic_boot_get_handlers(void) +{ + return &handlers; +} + +static void main_fiq(void) +{ + panic(); +} + +void console_init(void) +{ + pl011_init(&console_data, CONSOLE_UART_BASE, + CONSOLE_UART_CLK_IN_HZ, CONSOLE_BAUDRATE); + register_serial_console(&console_data.chip); +} diff --git a/core/arch/arm/plat-poplar/platform_config.h b/core/arch/arm/plat-poplar/platform_config.h new file mode 100644 index 00000000..fb885d72 --- /dev/null +++ b/core/arch/arm/plat-poplar/platform_config.h @@ -0,0 +1,151 @@ +/* + * Copyright (c) 2017, Linaro Limited + * SPDX-License-Identifier: BSD-2-Clause + */ + +#ifndef PLATFORM_CONFIG_H +#define PLATFORM_CONFIG_H + +#include <hi3798cv200.h> + +/* Make stacks aligned to data cache line length */ +#define STACK_ALIGNMENT 64 + +/* PL011 UART */ +#define CONSOLE_UART_BASE PL011_UART0_BASE +#define CONSOLE_BAUDRATE PL011_BAUDRATE +#define CONSOLE_UART_CLK_IN_HZ PL011_UART0_CLK_IN_HZ + +/* + * Poplar memory map + * + * Note: the physical address ranges below correspond to DRAM which is + * non-secure by default. Therefore, the terms TZDRAM and TZSRAM may not + * reflect the reality and only indicate areas that "would normally be" + * secure DRAM and secure SRAM in a more complete implementation. + * The memory map was defined like this for lack of better documentation. + * It is good enough for development/testing purposes. + * + * 0xFF00_0000 [DRAM2_LIMIT] + * other (devmem) + * 0xF000_0000 [DRAM2_BASE] + + * 0x8000_0000 (0x4000_0000 for 1GB board) [DRAM0_LIMIT] + * u-boot + ree memory: 1144 MiB (144 MiB for 1GB board) + * 0x3700_0000 CONFIG_SYS_TEXT_BASE (u-boot) + * PLAT_POPLAR_NS_IMAGE_OFFSET (arm-tf) + * ramdisk: 76 MiB + * 0x3240_0000 + * fdt: 2 MiB + * 0x3220_0000 + * pxe file or script addr: 2 MiB + * 0x3200_0000 + * kernel/android: 32 MiB + * 0x3000_0000 + * ree memory: 696 MiB + * 0x0480_0000 CONFIG_SYS_LOAD_ADDR (defined in u-boot) + * other: 6 MiB + * 0x0420_0000 CONFIG_SYS_INIT_SP_ADDR (defined in u-boot) + * 0x0408_0000 KERNEL_TEXT_OFFSET (defined in u-boot) + * unused: 512 KiB + * 0x0400_0000 + + * 0x0400_0000 - + * TA RAM: 14 MiB | TZDRAM + * 0x0320_0000 - + + * CFG_WITH_PAGER=n - + * TEE RAM: 2 MiB (CFG_TEE_RAM_VA_SIZE) | TZDRAM + * 0x0300_0000 [TZDRAM_BASE, CFG_TEE_LOAD_ADDR] - + * + * CFG_WITH_PAGER=y + * Unused + * 0x030A_0000 - + * TEE RAM: 640 KiB (TZSRAM_SIZE) | TZSRAM + * 0x0300_0000 [TZSRAM_BASE, CFG_TEE_LOAD_ADDR] - + + * 0x0300_0000 [TZDRAM_BASE, TZSRAM_BASE, CFG_TEE_LOAD_ADDR] + * OP-TEE Future Use: 4 MiB + * 0x02C0_0000 + + * 0x02C0_0000 + * Secure Data Path buffers: 4 MiB + * 0x0280_0000 [CFG_TEE_SDP_MEM_BASE] + * Shared memory: 4 MiB + * 0x0240_0000 + * OP-TEE Future Use: 2 MiB + * 0x0220_0000 + + * 0x0220_0000 + * unused: 64 KiB + * 0x021F_0000 l-loader limit (len/size set by poplar-l-loader.git) + * unused (cannot be used) + * 0x0210_0000 l-loader limit (max bootrom can accept) + * fip.bin load zone: 768 KiB + * 0x0204_0000 + * bl31: 80 KiB + * 0x0202_A000 + * bl2: 48 KiB + * 0x0201_E000 + * bl1: 64 KiB + * 0x0200_E000 + * l-loader text: 52 KiB + * 0x0200_1000 + * unused + * 0x0200_0000 + * TA virtual memory space + * 0x0000_0000 [DRAM0_BASE] + */ +#define DRAM0_BASE 0x00000000 +#if (CFG_DRAM_SIZE_GB == 2) +#define DRAM0_SIZE 0x80000000 +#elif (CFG_DRAM_SIZE_GB == 1) +#define DRAM0_SIZE 0x40000000 +#else +#error Unsupported DRAM size +#endif + +#define DRAM0_BASE_NSEC 0x04080000 +#define DRAM0_SIZE_NSEC (DRAM0_SIZE - DRAM0_BASE_NSEC) + +#define DRAM2_BASE 0xF0000000 +#define DRAM2_SIZE 0x0F000000 + +#ifdef CFG_WITH_PAGER + +#define TZSRAM_BASE 0x03000000 +#define TZSRAM_SIZE CFG_CORE_TZSRAM_EMUL_SIZE + +#define TZDRAM_BASE 0x03200000 +#define TZDRAM_SIZE (14 * 1024 * 1024) + +#define CFG_TEE_RAM_START TZSRAM_BASE +#define CFG_TEE_RAM_PH_SIZE TZSRAM_SIZE +#define CFG_TA_RAM_START ROUNDUP(TZDRAM_BASE, CORE_MMU_DEVICE_SIZE) +#define CFG_TA_RAM_SIZE ROUNDDOWN(TZDRAM_SIZE, CORE_MMU_DEVICE_SIZE) + +#else /* CFG_WITH_PAGER */ + +#define TZDRAM_BASE 0x03000000 +#define TZDRAM_SIZE (16 * 1024 * 1024) + +#define CFG_TEE_RAM_START TZDRAM_BASE +#define CFG_TEE_RAM_PH_SIZE CFG_TEE_RAM_VA_SIZE +#define CFG_TA_RAM_START ROUNDUP((TZDRAM_BASE + CFG_TEE_RAM_VA_SIZE), \ + CORE_MMU_DEVICE_SIZE) + +#define CFG_TA_RAM_SIZE ROUNDDOWN((TZDRAM_SIZE - CFG_TEE_RAM_VA_SIZE),\ + CORE_MMU_DEVICE_SIZE) + +#endif /* CFG_WITH_PAGER */ + +#define CFG_SHMEM_START 0x02400000 +#define CFG_SHMEM_SIZE (4 * 1024 * 1024) + +#define CFG_TEE_CORE_NB_CORE 4 + +#define CFG_TEE_RAM_VA_SIZE (2 * 1024 * 1024) + +#define CFG_TEE_LOAD_ADDR 0x03000000 /* BL32_BASE */ + +#endif /* PLATFORM_CONFIG_H */ diff --git a/core/arch/arm/plat-poplar/sub.mk b/core/arch/arm/plat-poplar/sub.mk new file mode 100644 index 00000000..8ddc2fd4 --- /dev/null +++ b/core/arch/arm/plat-poplar/sub.mk @@ -0,0 +1,2 @@ +global-incdirs-y += . +srcs-y += main.c |