diff options
| author | Etienne Carriere <etienne.carriere@linaro.org> | 2019-02-12 17:42:31 +0100 |
|---|---|---|
| committer | Jérôme Forissier <jerome.forissier@linaro.org> | 2019-02-14 15:17:43 +0100 |
| commit | 79f948c601aa6a89a63d6ec2d76cd0050abd5d9c (patch) | |
| tree | d6b78fa51b6452ce9a6087f44685fa1f6f7d6d87 /core | |
| parent | 5dbc88e3e9ae1e675aebda1e48d13e83f4df76e7 (diff) | |
stm: upgrade from write32() to io_write32() and friends
Replace use of readX() and writeX() with io_readX() and io_writeX().
The former are about to be deprecated in favor to the later.
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Diffstat (limited to 'core')
| -rw-r--r-- | core/arch/arm/plat-stm/main.c | 30 | ||||
| -rw-r--r-- | core/arch/arm/plat-stm/rng_support.c | 4 |
2 files changed, 17 insertions, 17 deletions
diff --git a/core/arch/arm/plat-stm/main.c b/core/arch/arm/plat-stm/main.c index ff862b0e..77c87e5c 100644 --- a/core/arch/arm/plat-stm/main.c +++ b/core/arch/arm/plat-stm/main.c @@ -116,14 +116,14 @@ vaddr_t pl310_base(void) void arm_cl2_config(vaddr_t pl310) { /* pl310 off */ - write32(0, pl310 + PL310_CTRL); + io_write32(pl310 + PL310_CTRL, 0); /* config PL310 */ - write32(PL310_TAG_RAM_CTRL_INIT, pl310 + PL310_TAG_RAM_CTRL); - write32(PL310_DATA_RAM_CTRL_INIT, pl310 + PL310_DATA_RAM_CTRL); - write32(PL310_AUX_CTRL_INIT, pl310 + PL310_AUX_CTRL); - write32(PL310_PREFETCH_CTRL_INIT, pl310 + PL310_PREFETCH_CTRL); - write32(PL310_POWER_CTRL_INIT, pl310 + PL310_POWER_CTRL); + io_write32(pl310 + PL310_TAG_RAM_CTRL, PL310_TAG_RAM_CTRL_INIT); + io_write32(pl310 + PL310_DATA_RAM_CTRL, PL310_DATA_RAM_CTRL_INIT); + io_write32(pl310 + PL310_AUX_CTRL, PL310_AUX_CTRL_INIT); + io_write32(pl310 + PL310_PREFETCH_CTRL, PL310_PREFETCH_CTRL_INIT); + io_write32(pl310 + PL310_POWER_CTRL, PL310_POWER_CTRL_INIT); /* invalidate all pl310 cache ways */ arm_cl2_invbyway(pl310); @@ -141,19 +141,19 @@ void plat_cpu_reset_late(void) if (get_core_pos()) return; - write32(SCU_SAC_INIT, SCU_BASE + SCU_SAC); - write32(SCU_NSAC_INIT, SCU_BASE + SCU_NSAC); - write32(CPU_PORT_FILT_END, SCU_BASE + SCU_FILT_EA); - write32(CPU_PORT_FILT_START, SCU_BASE + SCU_FILT_SA); - write32(SCU_CTRL_INIT, SCU_BASE + SCU_CTRL); + io_write32(SCU_BASE + SCU_SAC, SCU_SAC_INIT); + io_write32(SCU_BASE + SCU_NSAC, SCU_NSAC_INIT); + io_write32(SCU_BASE + SCU_FILT_EA, CPU_PORT_FILT_END); + io_write32(SCU_BASE + SCU_FILT_SA, CPU_PORT_FILT_START); + io_write32(SCU_BASE + SCU_CTRL, SCU_CTRL_INIT); - write32(CPU_PORT_FILT_END, pl310_base() + PL310_ADDR_FILT_END); - write32(CPU_PORT_FILT_START | PL310_CTRL_ENABLE_BIT, - pl310_base() + PL310_ADDR_FILT_START); + io_write32(pl310_base() + PL310_ADDR_FILT_END, CPU_PORT_FILT_END); + io_write32(pl310_base() + PL310_ADDR_FILT_START, + CPU_PORT_FILT_START | PL310_CTRL_ENABLE_BIT); /* TODO: gic_init scan fails, pre-init all SPIs are nonsecure */ for (i = 0; i < (31 * 4); i += 4) - write32(0xFFFFFFFF, GIC_DIST_BASE + GIC_DIST_ISR1 + i); + io_write32(GIC_DIST_BASE + GIC_DIST_ISR1 + i, 0xFFFFFFFF); } void main_init_gic(void) diff --git a/core/arch/arm/plat-stm/rng_support.c b/core/arch/arm/plat-stm/rng_support.c index 478d9f8e..aba047fd 100644 --- a/core/arch/arm/plat-stm/rng_support.c +++ b/core/arch/arm/plat-stm/rng_support.c @@ -37,7 +37,7 @@ static inline int hwrng_waithost_fifo_full(void) uint32_t status; do { - status = read32(rng_base() + RNG_STATUS_OFFSET); + status = io_read32(rng_base() + RNG_STATUS_OFFSET); } while (!(status & RNG_STATUS_FULL)); if (status & (RNG_STATUS_ERR0 | RNG_STATUS_ERR1)) @@ -109,7 +109,7 @@ uint8_t hw_get_random_byte(void) /* Read the FIFO according the number of expected element */ for (i = 0; i < _LOCAL_FIFO_SIZE / 2; i++) - tmpval[i] = read32(rng_base() + RNG_VAL_OFFSET) & 0xFFFF; + tmpval[i] = io_read32(rng_base() + RNG_VAL_OFFSET) & 0xFFFF; /* Update the local SW fifo for next request */ pos = 0; |