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authorEtienne Carriere <etienne.carriere@linaro.org>2019-04-04 11:17:24 +0200
committerJérôme Forissier <jerome.forissier@linaro.org>2019-04-04 18:15:32 +0700
commit63c46642ceeb0b4db8a8164718cb230328b87892 (patch)
tree7374b04bef35a713bda0a1f2f5f1862b4b4aaeb1 /core
parentc0c3a02055b7a3b27dd2cbac6c481f34e0d1f4cb (diff)
stm32_uart: assert clock and register base address
Assert clock and UART base address were found from DTB instead of panicking. This can help debugging. Invalid clock or iomem base address already lead to core panic, an assertion here is far enough. Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org> Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org> Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Diffstat (limited to 'core')
-rw-r--r--core/drivers/stm32_uart.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/core/drivers/stm32_uart.c b/core/drivers/stm32_uart.c
index d0c4594e..30700e5a 100644
--- a/core/drivers/stm32_uart.c
+++ b/core/drivers/stm32_uart.c
@@ -115,8 +115,8 @@ struct stm32_uart_pdata *stm32_uart_init_from_dt_node(void *fdt, int node)
if (info.status == DT_STATUS_DISABLED)
return NULL;
- if (info.clock < 0)
- panic();
+ assert(info.clock != DT_INFO_INVALID_CLOCK &&
+ info.reg != DT_INFO_INVALID_REG);
pd = calloc(1, sizeof(*pd));
if (!pd)