diff options
| author | Etienne Carriere <etienne.carriere@linaro.org> | 2019-02-12 17:40:00 +0100 |
|---|---|---|
| committer | Jérôme Forissier <jerome.forissier@linaro.org> | 2019-02-14 15:17:43 +0100 |
| commit | 918bb3a5f3e473ec252ff2dfb71d666108dd22f4 (patch) | |
| tree | 08c5a956c5d635c0061dacc219dfd429fa3d51bb /core/drivers/stm32_gpio.c | |
| parent | b7d2b849d59b9cbbd0fc0cb01b5c3f2a862510ec (diff) | |
core: upgrade from write32() to io_write32() and friends
Replace use of readX() and writeX() with io_readX() and io_writeX().
The former function are about to be deprecated in favor to the later.
This change upgrades core generic code and drivers.
At some place, io_clrbitsX(), io_setbitsX() and io_clrsetbitsX()
replace the writeX(readX() ...) operations when obvious.
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Diffstat (limited to 'core/drivers/stm32_gpio.c')
| -rw-r--r-- | core/drivers/stm32_gpio.c | 22 |
1 files changed, 11 insertions, 11 deletions
diff --git a/core/drivers/stm32_gpio.c b/core/drivers/stm32_gpio.c index ea4ab00b..da5c5f92 100644 --- a/core/drivers/stm32_gpio.c +++ b/core/drivers/stm32_gpio.c @@ -66,24 +66,24 @@ static void get_gpio_cfg(uint32_t bank, uint32_t pin, struct gpio_cfg *cfg) * 4bit fields are accessed at bit position being fourth the pin index * but accessed from 2 32bit registers at incremental addresses. */ - cfg->mode = (read32(base + GPIO_MODER_OFFSET) >> (pin << 1)) & + cfg->mode = (io_read32(base + GPIO_MODER_OFFSET) >> (pin << 1)) & GPIO_MODE_MASK; - cfg->otype = (read32(base + GPIO_OTYPER_OFFSET) >> pin) & 1; + cfg->otype = (io_read32(base + GPIO_OTYPER_OFFSET) >> pin) & 1; - cfg->ospeed = (read32(base + GPIO_OSPEEDR_OFFSET) >> (pin << 1)) & + cfg->ospeed = (io_read32(base + GPIO_OSPEEDR_OFFSET) >> (pin << 1)) & GPIO_OSPEED_MASK; - cfg->pupd = (read32(base + GPIO_PUPDR_OFFSET) >> (pin << 1)) & + cfg->pupd = (io_read32(base + GPIO_PUPDR_OFFSET) >> (pin << 1)) & GPIO_PUPD_PULL_MASK; - cfg->od = (read32(base + GPIO_ODR_OFFSET) >> (pin << 1)) & 1; + cfg->od = (io_read32(base + GPIO_ODR_OFFSET) >> (pin << 1)) & 1; if (pin < GPIO_ALT_LOWER_LIMIT) - cfg->af = (read32(base + GPIO_AFRL_OFFSET) >> (pin << 2)) & + cfg->af = (io_read32(base + GPIO_AFRL_OFFSET) >> (pin << 2)) & GPIO_ALTERNATE_MASK; else - cfg->af = (read32(base + GPIO_AFRH_OFFSET) >> + cfg->af = (io_read32(base + GPIO_AFRH_OFFSET) >> ((pin - GPIO_ALT_LOWER_LIMIT) << 2)) & GPIO_ALTERNATE_MASK; @@ -354,7 +354,7 @@ static __maybe_unused bool valid_gpio_config(unsigned int bank, unsigned int pin, bool input) { vaddr_t base = stm32_get_gpio_bank_base(bank); - uint32_t mode = (read32(base + GPIO_MODER_OFFSET) >> (pin << 1)) & + uint32_t mode = (io_read32(base + GPIO_MODER_OFFSET) >> (pin << 1)) & GPIO_MODE_MASK; if (pin > GPIO_PIN_MAX) @@ -376,7 +376,7 @@ int stm32_gpio_get_input_level(unsigned int bank, unsigned int pin) stm32_clock_enable(clock); - if (read32(base + GPIO_IDR_OFFSET) == BIT(pin)) + if (io_read32(base + GPIO_IDR_OFFSET) == BIT(pin)) rc = 1; stm32_clock_disable(clock); @@ -394,9 +394,9 @@ void stm32_gpio_set_output_level(unsigned int bank, unsigned int pin, int level) stm32_clock_enable(clock); if (level) - write32(BIT(pin), base + GPIO_BSRR_OFFSET); + io_write32(base + GPIO_BSRR_OFFSET, BIT(pin)); else - write32(BIT(pin + 16), base + GPIO_BSRR_OFFSET); + io_write32(base + GPIO_BSRR_OFFSET, BIT(pin + 16)); stm32_clock_disable(clock); } |