core: upgrade from write32() to io_write32() and friends

Replace use of readX() and writeX() with io_readX() and io_writeX().
The former function are about to be deprecated in favor to the later.

This change upgrades core generic code and drivers.
At some place, io_clrbitsX(), io_setbitsX() and io_clrsetbitsX()
replace the writeX(readX() ...) operations when obvious.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

1 files changed, 18 insertions, 30 deletions

diff --git a/core/drivers/pl061_gpio.c b/core/drivers/pl061_gpio.c
index a4bdb35b..95e9571a 100644
--- a/core/drivers/pl061_gpio.c
+++ b/core/drivers/pl061_gpio.c
@@ -49,7 +49,7 @@ static enum gpio_dir pl061_get_direction(unsigned int gpio_pin)
 
 	base_addr = pl061_reg_base[gpio_pin / GPIOS_PER_PL061];
 	offset = gpio_pin % GPIOS_PER_PL061;
-	data = read8(base_addr + GPIODIR);
+	data = io_read8(base_addr + GPIODIR);
 	if (data & BIT(offset))
 		return GPIO_DIR_OUT;
 	return GPIO_DIR_IN;
@@ -58,20 +58,16 @@ static enum gpio_dir pl061_get_direction(unsigned int gpio_pin)
 static void pl061_set_direction(unsigned int gpio_pin, enum gpio_dir direction)
 {
 	vaddr_t base_addr;
-	uint8_t data;
 	unsigned int offset;
 
 	assert(gpio_pin < PLAT_PL061_MAX_GPIOS);
 
 	base_addr = pl061_reg_base[gpio_pin / GPIOS_PER_PL061];
 	offset = gpio_pin % GPIOS_PER_PL061;
-	if (direction == GPIO_DIR_OUT) {
-		data = read8(base_addr + GPIODIR) | BIT(offset);
-		write8(data, base_addr + GPIODIR);
-	} else {
-		data = read8(base_addr + GPIODIR) & ~BIT(offset);
-		write8(data, base_addr + GPIODIR);
-	}
+	if (direction == GPIO_DIR_OUT)
+		io_setbits8(base_addr + GPIODIR, BIT(offset));
+	else
+		io_clrbits8(base_addr + GPIODIR, BIT(offset));
 }
 
 /*
@@ -91,7 +87,7 @@ static enum gpio_level pl061_get_value(unsigned int gpio_pin)
 
 	base_addr = pl061_reg_base[gpio_pin / GPIOS_PER_PL061];
 	offset = gpio_pin % GPIOS_PER_PL061;
-	if (read8(base_addr + BIT(offset + 2)))
+	if (io_read8(base_addr + BIT(offset + 2)))
 		return GPIO_LEVEL_HIGH;
 	return GPIO_LEVEL_LOW;
 }
@@ -111,9 +107,9 @@ static void pl061_set_value(unsigned int gpio_pin, enum gpio_level value)
 	base_addr = pl061_reg_base[gpio_pin / GPIOS_PER_PL061];
 	offset = gpio_pin % GPIOS_PER_PL061;
 	if (value == GPIO_LEVEL_HIGH)
-		write8(BIT(offset), base_addr + BIT(offset + 2));
+		io_write8(base_addr + BIT(offset + 2), BIT(offset));
 	else
-		write8(0, base_addr + BIT(offset + 2));
+		io_write8(base_addr + BIT(offset + 2), 0);
 }
 
 static enum gpio_interrupt pl061_get_interrupt(unsigned int gpio_pin)
@@ -126,7 +122,7 @@ static enum gpio_interrupt pl061_get_interrupt(unsigned int gpio_pin)
 
 	base_addr = pl061_reg_base[gpio_pin / GPIOS_PER_PL061];
 	offset = gpio_pin % GPIOS_PER_PL061;
-	data = read8(base_addr + GPIOIE);
+	data = io_read8(base_addr + GPIOIE);
 	if (data & BIT(offset))
 		return GPIO_INTERRUPT_ENABLE;
 	return GPIO_INTERRUPT_DISABLE;
@@ -136,20 +132,16 @@ static void pl061_set_interrupt(unsigned int gpio_pin,
 	enum gpio_interrupt ena_dis)
 {
 	vaddr_t base_addr;
-	uint8_t data;
 	unsigned int offset;
 
 	assert(gpio_pin < PLAT_PL061_MAX_GPIOS);
 
 	base_addr = pl061_reg_base[gpio_pin / GPIOS_PER_PL061];
 	offset = gpio_pin % GPIOS_PER_PL061;
-	if (ena_dis == GPIO_INTERRUPT_ENABLE) {
-		data = read8(base_addr + GPIOIE) | BIT(offset);
-		write8(data, base_addr + GPIOIE);
-	} else {
-		data = read8(base_addr + GPIOIE) & ~BIT(offset);
-		write8(data, base_addr + GPIOIE);
-	}
+	if (ena_dis == GPIO_INTERRUPT_ENABLE)
+		io_setbits8(base_addr + GPIOIE, BIT(offset));
+	else
+		io_clrbits8(base_addr + GPIOIE, BIT(offset));
 }
 
 /*
@@ -194,7 +186,7 @@ enum pl061_mode_control pl061_get_mode_control(unsigned int gpio_pin)
 
 	base_addr = pl061_reg_base[gpio_pin / GPIOS_PER_PL061];
 	offset = gpio_pin % GPIOS_PER_PL061;
-	data = read8(base_addr + GPIOAFSEL);
+	data = io_read8(base_addr + GPIOAFSEL);
 	if (data & BIT(offset))
 		return PL061_MC_HW;
 	return PL061_MC_SW;
@@ -204,18 +196,14 @@ void pl061_set_mode_control(unsigned int gpio_pin,
 	enum pl061_mode_control hw_sw)
 {
 	vaddr_t base_addr;
-	uint8_t data;
 	unsigned int offset;
 
 	assert(gpio_pin < PLAT_PL061_MAX_GPIOS);
 
 	base_addr = pl061_reg_base[gpio_pin / GPIOS_PER_PL061];
 	offset = gpio_pin % GPIOS_PER_PL061;
-	if (hw_sw == PL061_MC_HW) {
-		data = read8(base_addr + GPIOAFSEL) | BIT(offset);
-		write8(data, base_addr + GPIOAFSEL);
-	} else {
-		data = read8(base_addr + GPIOAFSEL) & ~BIT(offset);
-		write8(data, base_addr + GPIOAFSEL);
-	}
+	if (hw_sw == PL061_MC_HW)
+		io_setbits8(base_addr + GPIOAFSEL, BIT(offset));
+	else
+		io_clrbits8(base_addr + GPIOAFSEL, BIT(offset));
 }