diff options
| author | sunny <sunny@allwinnertech.com> | 2014-11-07 14:20:03 +0800 |
|---|---|---|
| committer | sunny <sunny@allwinnertech.com> | 2015-01-16 19:25:33 -0800 |
| commit | bedc2b9fafb3fe78e8176d5e0879ffd6eab52ea1 (patch) | |
| tree | 6a973095c794388f90a834ebd289f9a2ac246395 /core/drivers/gic.c | |
| parent | 80439f3865207ea998d64fb66c80bd04188c8722 (diff) | |
driver/gic: add gic_cpu_init interface.
The interface mainly use for secondary cpu bootup.
When secondary cpu bootup, It will initialize per-cpu gic-cpu-interface.
The gic_cpu_init main work include:
1.Set the per-cpu interrupts as Group1;
2.Enable Group0-interrupts/Group1-interrupts/FIQEn.
Signed-off-by: sunny <sunny@allwinnertech.com>
Reviewed-by: Joakim Bech <joakim.bech@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Pascal Brand <pascal.brand@linaro.org>
Diffstat (limited to 'core/drivers/gic.c')
| -rw-r--r-- | core/drivers/gic.c | 25 |
1 files changed, 24 insertions, 1 deletions
diff --git a/core/drivers/gic.c b/core/drivers/gic.c index 9670f300..51003cd9 100644 --- a/core/drivers/gic.c +++ b/core/drivers/gic.c @@ -110,6 +110,20 @@ out: return ret; } +void gic_cpu_init(void) +{ + /* per-CPU inerrupts config: + * ID0-ID7(SGI) for Non-secure interrupts + * ID8-ID15(SGI) for Secure interrupts. + * All PPI config as Non-secure interrupts. + */ + write32(0xffff00ff, gic.gicd_base + GICD_IGROUPR(0)); + + /* Enable GIC */ + write32(GICC_CTLR_ENABLEGRP0 | GICC_CTLR_ENABLEGRP1 | GICC_CTLR_FIQEN, + gic.gicc_base + GICC_CTLR); +} + void gic_init(vaddr_t gicc_base, vaddr_t gicd_base) { size_t n; @@ -126,7 +140,16 @@ void gic_init(vaddr_t gicc_base, vaddr_t gicd_base) write32(0xffffffff, gic.gicd_base + GICD_ICPENDR(n)); /* Mark interrupts non-secure */ - write32(0xffffffff, gic.gicd_base + GICD_IGROUPR(n)); + if (n == 0) { + /* per-CPU inerrupts config: + * ID0-ID7(SGI) for Non-secure interrupts + * ID8-ID15(SGI) for Secure interrupts. + * All PPI config as Non-secure interrupts. + */ + write32(0xffff00ff, gic.gicd_base + GICD_IGROUPR(n)); + } else { + write32(0xffffffff, gic.gicd_base + GICD_IGROUPR(n)); + } } /* Enable GIC */ |