assert/panic: fix misuse of assert/panic

Currently implementation of macro assert() does not expand to a
no-op when NDEBUG is defined. This will be done in a later change.
Before that, fix misuses of assert() and TEE_ASSERT():
- Correct misplaced assert() that should panic() whatever NDEBUG.
- Correct misplaced TEE_ASSERT() that should simply assert().

Also cleanup many inclusions of "assert.h" and few calls of assert().

Signed-off-by: Jens Wiklander <jen.wiklander@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Tested-by: Etienne Carriere <etienne.carriere@linaro.org> (QEMU)

1 files changed, 9 insertions, 12 deletions

diff --git a/core/drivers/gic.c b/core/drivers/gic.c
index 10f93c3e..4ec581fc 100644
--- a/core/drivers/gic.c
+++ b/core/drivers/gic.c
@@ -26,14 +26,14 @@
  * POSSIBILITY OF SUCH DAMAGE.
  */
 
+#include <assert.h>
 #include <drivers/gic.h>
 #include <kernel/interrupt.h>
+#include <kernel/tee_common_unpg.h>
 #include <util.h>
 #include <io.h>
 #include <trace.h>
 
-#include <assert.h>
-
 /* Offsets from gic.gicc_base */
 #define GICC_CTLR		(0x000)
 #define GICC_PMR		(0x004)
@@ -194,8 +194,6 @@ static void gic_it_add(struct gic_data *gd, size_t it)
 	size_t idx = it / NUM_INTS_PER_REG;
 	uint32_t mask = 1 << (it % NUM_INTS_PER_REG);
 
-	assert(it <= gd->max_it); /* Not too large */
-
 	/* Disable the interrupt */
 	write32(mask, gd->gicd_base + GICD_ICENABLER(idx));
 	/* Make it non-pending */
@@ -208,11 +206,10 @@ static void gic_it_add(struct gic_data *gd, size_t it)
 static void gic_it_set_cpu_mask(struct gic_data *gd, size_t it,
 				uint8_t cpu_mask)
 {
-	size_t idx = it / NUM_INTS_PER_REG;
-	uint32_t mask = 1 << (it % NUM_INTS_PER_REG);
+	size_t idx __maybe_unused = it / NUM_INTS_PER_REG;
+	uint32_t mask __maybe_unused = 1 << (it % NUM_INTS_PER_REG);
 	uint32_t target, target_shift;
 
-	assert(it <= gd->max_it); /* Not too large */
 	/* Assigned to group0 */
 	assert(!(read32(gd->gicd_base + GICD_IGROUPR(idx)) & mask));
 
@@ -232,10 +229,9 @@ static void gic_it_set_cpu_mask(struct gic_data *gd, size_t it,
 
 static void gic_it_set_prio(struct gic_data *gd, size_t it, uint8_t prio)
 {
-	size_t idx = it / NUM_INTS_PER_REG;
-	uint32_t mask = 1 << (it % NUM_INTS_PER_REG);
+	size_t idx __maybe_unused = it / NUM_INTS_PER_REG;
+	uint32_t mask __maybe_unused = 1 << (it % NUM_INTS_PER_REG);
 
-	assert(it <= gd->max_it); /* Not too large */
 	/* Assigned to group0 */
 	assert(!(read32(gd->gicd_base + GICD_IGROUPR(idx)) & mask));
 
@@ -250,7 +246,6 @@ static void gic_it_enable(struct gic_data *gd, size_t it)
 	size_t idx = it / NUM_INTS_PER_REG;
 	uint32_t mask = 1 << (it % NUM_INTS_PER_REG);
 
-	assert(it <= gd->max_it); /* Not too large */
 	/* Assigned to group0 */
 	assert(!(read32(gd->gicd_base + GICD_IGROUPR(idx)) & mask));
 	/* Not enabled yet */
@@ -265,7 +260,6 @@ static void gic_it_disable(struct gic_data *gd, size_t it)
 	size_t idx = it / NUM_INTS_PER_REG;
 	uint32_t mask = 1 << (it % NUM_INTS_PER_REG);
 
-	assert(it <= gd->max_it); /* Not too large */
 	/* Assigned to group0 */
 	assert(!(read32(gd->gicd_base + GICD_IGROUPR(idx)) & mask));
 
@@ -346,6 +340,7 @@ static void gic_op_add(struct itr_chip *chip, size_t it,
 {
 	struct gic_data *gd = container_of(chip, struct gic_data, chip);
 
+	TEE_ASSERT(it < gd->max_it);
 	gic_it_add(gd, it);
 	/* Set the CPU mask to deliver interrupts to any online core */
 	gic_it_set_cpu_mask(gd, it, 0xff);
@@ -356,6 +351,7 @@ static void gic_op_enable(struct itr_chip *chip, size_t it)
 {
 	struct gic_data *gd = container_of(chip, struct gic_data, chip);
 
+	TEE_ASSERT(it < gd->max_it);
 	gic_it_enable(gd, it);
 }
 
@@ -363,5 +359,6 @@ static void gic_op_disable(struct itr_chip *chip, size_t it)
 {
 	struct gic_data *gd = container_of(chip, struct gic_data, chip);
 
+	TEE_ASSERT(it < gd->max_it);
 	gic_it_disable(gd, it);
 }