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| author | Jens Wiklander <jens.wiklander@linaro.org> | 2015-03-19 15:41:27 +0100 |
|---|---|---|
| committer | Jens Wiklander <jens.wiklander@linaro.org> | 2015-04-01 09:43:00 +0200 |
| commit | 1f60363a2157d404764a700e960fb227dfb960f2 (patch) | |
| tree | fbe4ed7ae602e5a924ce78b84bdbef26607aaa49 /core/drivers/gic.c | |
| parent | 5c550d599aa3a2a90f3ea403abf43fad656dce19 (diff) | |
select base types based on ILP32 and LP64 defines
* Selects base types base on the __ILP32__ and __LP64__ defines
* Fixes warnings from change of base types
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (QEMU)
Reviewed-by: Pascal Brand <pascal.brand@linaro.org>
Diffstat (limited to 'core/drivers/gic.c')
| -rw-r--r-- | core/drivers/gic.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/core/drivers/gic.c b/core/drivers/gic.c index 51003cd9..d5bcd5cf 100644 --- a/core/drivers/gic.c +++ b/core/drivers/gic.c @@ -197,7 +197,7 @@ void gic_it_set_cpu_mask(size_t it, uint8_t cpu_mask) target_shift = (it % NUM_TARGETS_PER_REG) * ITARGETSR_FIELD_BITS; target &= ~(ITARGETSR_FIELD_MASK << target_shift); target |= cpu_mask << target_shift; - DMSG("cpu_mask: writing 0x%x to 0x%x\n", + DMSG("cpu_mask: writing 0x%x to 0x%" PRIxVA, target, gic.gicd_base + GICD_ITARGETSR(it / NUM_TARGETS_PER_REG)); write32(target, gic.gicd_base + GICD_ITARGETSR(it / NUM_TARGETS_PER_REG)); DMSG("cpu_mask: 0x%x\n", @@ -214,7 +214,7 @@ void gic_it_set_prio(size_t it, uint8_t prio) assert(!(read32(gic.gicd_base + GICD_IGROUPR(idx)) & mask)); /* Set prio it to selected CPUs */ - DMSG("prio: writing 0x%x to 0x%x\n", + DMSG("prio: writing 0x%x to 0x%" PRIxVA, prio, gic.gicd_base + GICD_IPRIORITYR(0) + it); write8(prio, gic.gicd_base + GICD_IPRIORITYR(0) + it); } |