diff options
| author | Etienne Carriere <etienne.carriere@linaro.org> | 2017-03-14 15:42:57 +0100 |
|---|---|---|
| committer | Etienne Carriere <etienne.carriere@linaro.org> | 2017-03-14 15:43:33 +0100 |
| commit | a0c170d098db04249bb70b88d62ddd1d53101ca3 (patch) | |
| tree | e522904fe16897b0540ecd4c873e79eb9d71f104 /core/arch/arm/plat-zynq7k | |
| parent | 5c42fc056638915835d3a09bcb907c91145482f4 (diff) | |
plat-zynq7k: fix NSACR initialization
Bits #9..#0 of CPU register NSACR are specified by ARM as SBZP ("Set
Bit to Zero or Preserve on write"). This change fixes plat-zynq7k to
conform with the specs.
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Diffstat (limited to 'core/arch/arm/plat-zynq7k')
| -rw-r--r-- | core/arch/arm/plat-zynq7k/plat_init.S | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/core/arch/arm/plat-zynq7k/plat_init.S b/core/arch/arm/plat-zynq7k/plat_init.S index 2b778576..8d06c538 100644 --- a/core/arch/arm/plat-zynq7k/plat_init.S +++ b/core/arch/arm/plat-zynq7k/plat_init.S @@ -96,7 +96,7 @@ UNWIND( .fnstart) mov_imm r0, 0x00000041 write_actlr r0 - mov_imm r0, 0x00020FFF + mov_imm r0, 0x00020C00 write_nsacr r0 mov_imm r0, 0x00000001 |