diff options
| author | Andrew F. Davis <afd@ti.com> | 2017-04-20 18:42:59 -0500 |
|---|---|---|
| committer | Jérôme Forissier <jerome.forissier@linaro.org> | 2017-04-28 18:13:35 +0200 |
| commit | e040af6cc36a9ae8587a4c718075ff84369749e3 (patch) | |
| tree | 1f74899f407b8499a0ee6ca2bc4cec8eca2752e2 /core/arch/arm/plat-ti | |
| parent | 2579b45c97ed73c7e5f850307d81b63fd4c63719 (diff) | |
plat-ti: Add secure paging support for DRA7xx/AM57xx
Add definitions for secure SRAM and DRAM space for builds with
CFG_WITH_PAGER enabled.
Signed-off-by: Andrew F. Davis <afd@ti.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Diffstat (limited to 'core/arch/arm/plat-ti')
| -rw-r--r-- | core/arch/arm/plat-ti/main.c | 1 | ||||
| -rw-r--r-- | core/arch/arm/plat-ti/platform_config.h | 26 |
2 files changed, 27 insertions, 0 deletions
diff --git a/core/arch/arm/plat-ti/main.c b/core/arch/arm/plat-ti/main.c index 78cef849..dea35a7a 100644 --- a/core/arch/arm/plat-ti/main.c +++ b/core/arch/arm/plat-ti/main.c @@ -54,6 +54,7 @@ static struct gic_data gic_data; static struct serial8250_uart_data console_data __early_bss; static uint8_t plat_huk[PLAT_HW_UNIQUE_KEY_LENGTH]; +register_phys_mem(MEM_AREA_RAM_SEC, TZDRAM_BASE, CFG_TEE_RAM_VA_SIZE); register_phys_mem(MEM_AREA_IO_SEC, SECRAM_BASE, SECRAM_SIZE); register_phys_mem(MEM_AREA_IO_SEC, GICC_BASE, GICC_SIZE); register_phys_mem(MEM_AREA_IO_SEC, GICD_BASE, GICD_SIZE); diff --git a/core/arch/arm/plat-ti/platform_config.h b/core/arch/arm/plat-ti/platform_config.h index 1dee409c..f53daba0 100644 --- a/core/arch/arm/plat-ti/platform_config.h +++ b/core/arch/arm/plat-ti/platform_config.h @@ -37,6 +37,11 @@ #define TZDRAM_BASE 0xbdb00000 #define TZDRAM_SIZE 0x01c00000 +#ifdef CFG_WITH_PAGER +#define TZSRAM_BASE 0x40300000 +#define TZSRAM_SIZE (256 * 1024) +#endif /* CFG_WITH_PAGER */ + #define CFG_TEE_CORE_NB_CORE 2 #define UART1_BASE 0x4806A000 @@ -111,6 +116,25 @@ /* Make stacks aligned to data cache line length */ #define STACK_ALIGNMENT 64 +#ifdef CFG_WITH_PAGER +/* + * Use TZSRAM for TEE, page out everything else to TZDRAM. + * +--------+----------+ + * | DRAM | SHMEM | + * +--------+----------+ + * | | TA_RAM | + * | TZDRAM +----------+ + * | | PAGE_RAM | + * +--------+----------+ + * | TZSRAM | TEE_RAM | + * +--------+----------+ + */ +#define CFG_TEE_RAM_VA_SIZE (1 * 1024 * 1024) +#define CFG_TEE_RAM_PH_SIZE TZSRAM_SIZE +#define CFG_TEE_RAM_START TZSRAM_BASE +#define CFG_TEE_LOAD_ADDR (CFG_TEE_RAM_START + 0x1000) + +#else /* CFG_WITH_PAGER */ /* * Assumes that either TZSRAM isn't large enough or TZSRAM doesn't exist, * everything is in TZDRAM. @@ -127,6 +151,8 @@ #define CFG_TEE_RAM_START TZDRAM_BASE #define CFG_TEE_LOAD_ADDR (CFG_TEE_RAM_START + 0x100) +#endif /* CFG_WITH_PAGER */ + #define CFG_TA_RAM_START ROUNDUP((TZDRAM_BASE + CFG_TEE_RAM_VA_SIZE), \ CORE_MMU_DEVICE_SIZE) #define CFG_TA_RAM_SIZE ROUNDDOWN((TZDRAM_SIZE - CFG_TEE_RAM_VA_SIZE), \ |