diff options
| author | Bryan O'Donoghue <bryan.odonoghue@linaro.org> | 2018-11-19 15:30:28 +0000 |
|---|---|---|
| committer | Jérôme Forissier <jerome.forissier@linaro.org> | 2018-12-14 13:37:57 +0100 |
| commit | 0da41e90bb7d44317c32b78aec73e96951e14826 (patch) | |
| tree | c092412c5c856a683987f9bcd6b81d8d7069f979 /core/arch/arm/plat-imx | |
| parent | 7c1ee6aa87d49b299d4a7be6edbff94e1d68ad25 (diff) | |
arm: imx: add iMX7S WaARP7 MBL board definition
This patch adds an OP-TEE port for the i.MX7S WaRP7 for the MBED Linux OS
boot flow.
BootROM -> ATF/BL2
ATF -> FIP {u-boot, OPTEE}
OPTEE -> {populates DTB overlay}
u-boot -> FIT {DTB, Kernel, initramfs}
Merges DTB and OPTEE DTB-overlay
Linux
The current warp7 port looks like
BootROM -> u-boot
u-boot -> Load {Kernel, OPTEE, DTB}
OPTEE
Linux
In order to support the ATF bootflow a new port of OP-TEE with slightly
tweaked parameters is added here.
CFG_NS_ENTRY_ADDR = 0x87800000 is the entry point of u-boot
CFG_DT_OVERLAY = y adds DTB overlay fragments to the passed DTB
make PLATFORM=imx-mx7swarp7_mbl
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Diffstat (limited to 'core/arch/arm/plat-imx')
| -rw-r--r-- | core/arch/arm/plat-imx/conf.mk | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/core/arch/arm/plat-imx/conf.mk b/core/arch/arm/plat-imx/conf.mk index 1b7178ac..88fd7382 100644 --- a/core/arch/arm/plat-imx/conf.mk +++ b/core/arch/arm/plat-imx/conf.mk @@ -29,6 +29,7 @@ mx6s-flavorlist = \ mx7-flavorlist = \ mx7dsabresd \ mx7swarp7 \ + mx7swarp7_mbl \ mx7dclsom \ imx8mq-flavorlist = \ @@ -105,6 +106,16 @@ CFG_BOOT_SECONDARY_REQUEST ?= n $(call force,CFG_TEE_CORE_NB_CORE,1) endif +ifneq (,$(filter $(PLATFORM_FLAVOR),mx7swarp7_mbl)) +CFG_DDR_SIZE ?= 0x20000000 +CFG_NS_ENTRY_ADDR ?= 0x87800000 +CFG_DT_ADDR ?= 0x83100000 +CFG_BOOT_SECONDARY_REQUEST ?= n +CFG_EXTERNAL_DTB_OVERLAY = y +CFG_IMX_WDOG_EXT_RESET = y +$(call force,CFG_TEE_CORE_NB_CORE,1) +endif + ifneq (,$(filter $(PLATFORM_FLAVOR),mx6qsabresd mx6dlsabresd \ mx6dlsabrelite mx6dhmbedge mx6dlhmbedge)) CFG_DDR_SIZE ?= 0x40000000 |