diff options
| author | Peng Fan <peng.fan@nxp.com> | 2018-04-02 09:57:27 +0800 |
|---|---|---|
| committer | Joakim Bech <joakim.bech@linaro.org> | 2019-04-23 15:15:49 +0700 |
| commit | a75fcd2c63201dd0a565059e2a449bbf329c6444 (patch) | |
| tree | 2b1c44a6b39dc9665cca1fbd27cc6809624025e8 | |
| parent | 2976273f390e0654fb95928838ed0e251be8451f (diff) | |
core: arm: imx: a7: set L1 Data prefetch
The default value of L1PCTL field in ACTLR is 0x3, which is
"3 outstanding pre-fetches permitted", the value should not
be override with 0 to decrease the performance.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Rouven Czerwinski <r.czerwinski@pengutronix.de>
| -rw-r--r-- | core/arch/arm/plat-imx/a7_plat_init.S | 13 |
1 files changed, 11 insertions, 2 deletions
diff --git a/core/arch/arm/plat-imx/a7_plat_init.S b/core/arch/arm/plat-imx/a7_plat_init.S index 030f02d5..c65270f3 100644 --- a/core/arch/arm/plat-imx/a7_plat_init.S +++ b/core/arch/arm/plat-imx/a7_plat_init.S @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: BSD-2-Clause */ /* - * Copyright (c) 2017, NXP + * Copyright 2017-2019 NXP * * Peng Fan <peng.fan@nxp.com> */ @@ -34,7 +34,16 @@ FUNC plat_cpu_reset_early , : UNWIND( .fnstart) - mov_imm r0, 0x00000040 + /* + * DDI: Disable dual issue [bit28=0] + * DDVM: Disable Distributed Virtual Memory transactions [bit15=0] + * L1PCTL: L1 Data prefetch control [bit14:13=2b11] + * L1RADIS: L1 Data Cache read-allocate mode disable [bit12=0] + * L2RADIS: L2 Data Cache read-allocate mode disable [bit11=0] + * DODMBS: Disable optimized data memory barrier behavior [bit10=0] + * SMP: Enables coherent requests to the processor [bit6=0] + */ + mov_imm r0, 0x00006040 write_actlr r0 mov_imm r0, 0x00040C00 |