core: remove CFG_ prefix from TEE_RAM_START/VA_SIZE/PH_SIZE

Almost platform currently define these directives from within the source code, through platform_config.h. These values do not need to be configuration directive with the CFG_ prefix. This change renames these macros so that they do not mess with the platform configuration directives. Old macro label New macro label CFG_TEE_RAM_START TEE_RAM_START CFG_TEE_RAM_VA_SIZE TEE_RAM_VA_SIZE CFG_TEE_RAM_PH_SIZE TEE_RAM_PH_SIZE Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org> Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
author: Etienne Carriere <etienne.carriere@linaro.org> 2018-04-25 15:24:25 +0200
committer: Jérôme Forissier <jerome.forissier@linaro.org> 2018-04-25 18:26:18 +0200
commit: 446cc62a848e343a9d08e23476ba102fbc02065f (patch)
tree: d9a032b883659553255e229dfa2ee17c57c3d196
parent: 847b6aa6bb4abda37ec00c23cc2b53564c02ed29 (diff)
28 files changed, 186 insertions, 193 deletions
diff --git a/core/arch/arm/include/mm/core_mmu.h b/core/arch/arm/include/mm/core_mmu.h
index a095a2df..a0abce02 100644
--- a/core/arch/arm/include/mm/core_mmu.h
+++ b/core/arch/arm/include/mm/core_mmu.h
@@ -74,8 +74,8 @@
 #define CORE_MMU_USER_PARAM_SIZE	(1 << CORE_MMU_USER_PARAM_SHIFT)
 #define CORE_MMU_USER_PARAM_MASK	(CORE_MMU_USER_PARAM_SIZE - 1)
 
-#ifndef CFG_TEE_RAM_VA_SIZE
-#define CFG_TEE_RAM_VA_SIZE		CORE_MMU_PGDIR_SIZE
+#ifndef TEE_RAM_VA_SIZE
+#define TEE_RAM_VA_SIZE			CORE_MMU_PGDIR_SIZE
 #endif
 
 /*
@@ -97,9 +97,9 @@
 /*
  * Identify mapping constraint: virtual base address is the physical start addr.
  */
-#define TEE_RAM_VA_START		CFG_TEE_RAM_START
+#define TEE_RAM_VA_START		TEE_RAM_START
 #define TEE_TEXT_VA_START		(TEE_RAM_VA_START + \
-				(CFG_TEE_LOAD_ADDR - CFG_TEE_RAM_START))
+					(CFG_TEE_LOAD_ADDR - TEE_RAM_START))
 
 #ifndef STACK_ALIGNMENT
 #define STACK_ALIGNMENT			(sizeof(long) * 2)
diff --git a/core/arch/arm/kernel/generic_boot.c b/core/arch/arm/kernel/generic_boot.c
index bce86acc..6415860e 100644
--- a/core/arch/arm/kernel/generic_boot.c
+++ b/core/arch/arm/kernel/generic_boot.c
@@ -189,7 +189,7 @@ static void init_asan(void)
 	 */
 
 #define __ASAN_SHADOW_START \
-	ROUNDUP(TEE_RAM_VA_START + (CFG_TEE_RAM_VA_SIZE * 8) / 9 - 8, 8)
+	ROUNDUP(TEE_RAM_VA_START + (TEE_RAM_VA_SIZE * 8) / 9 - 8, 8)
 	assert(__ASAN_SHADOW_START == (vaddr_t)&__asan_shadow_start);
 #define __CFG_ASAN_SHADOW_OFFSET \
 	(__ASAN_SHADOW_START - (TEE_RAM_VA_START / 8))
@@ -270,7 +270,7 @@ static void carve_out_asan_mem(tee_mm_pool_t *pool __unused)
 static void init_vcore(tee_mm_pool_t *mm_vcore)
 {
 	const vaddr_t begin = TEE_RAM_VA_START;
-	vaddr_t end = TEE_RAM_VA_START + CFG_TEE_RAM_VA_SIZE;
+	vaddr_t end = TEE_RAM_VA_START + TEE_RAM_VA_SIZE;
 
 #ifdef CFG_CORE_SANITIZE_KADDRESS
 	/* Carve out asan memory, flat maped after core memory */
diff --git a/core/arch/arm/kernel/kern.ld.S b/core/arch/arm/kernel/kern.ld.S
index 9a7c4f7f..f4eb8352 100644
--- a/core/arch/arm/kernel/kern.ld.S
+++ b/core/arch/arm/kernel/kern.ld.S
@@ -63,9 +63,9 @@
  * TEE_RAM_VA_START:            The start virtual address of the TEE RAM
  * TEE_TEXT_VA_START:           The start virtual address of the OP-TEE text
  */
-#define TEE_RAM_VA_START                CFG_TEE_RAM_START
-#define TEE_TEXT_VA_START               (TEE_RAM_VA_START + \
-			(CFG_TEE_LOAD_ADDR - CFG_TEE_RAM_START))
+#define TEE_RAM_VA_START        TEE_RAM_START
+#define TEE_TEXT_VA_START       (TEE_RAM_VA_START + \
+					(CFG_TEE_LOAD_ADDR - TEE_RAM_START))
 
 OUTPUT_FORMAT(CFG_KERN_LINKER_FORMAT)
 OUTPUT_ARCH(CFG_KERN_LINKER_ARCH)
@@ -405,24 +405,24 @@ SECTIONS
 
 	__init_mem_usage = __tmp_hashes_end - TEE_TEXT_VA_START;
 
-	ASSERT(CFG_TEE_LOAD_ADDR >= CFG_TEE_RAM_START,
+	ASSERT(CFG_TEE_LOAD_ADDR >= TEE_RAM_START,
 		"Load address before start of physical memory")
-	ASSERT(CFG_TEE_LOAD_ADDR < (CFG_TEE_RAM_START + CFG_TEE_RAM_PH_SIZE),
+	ASSERT(CFG_TEE_LOAD_ADDR < (TEE_RAM_START + TEE_RAM_PH_SIZE),
 		"Load address after end of physical memory")
-	ASSERT(__tmp_hashes_end < (TEE_RAM_VA_START + CFG_TEE_RAM_PH_SIZE),
+	ASSERT(__tmp_hashes_end < (TEE_RAM_VA_START + TEE_RAM_PH_SIZE),
 		"OP-TEE can't fit init part into available physical memory")
-	ASSERT((TEE_RAM_VA_START + CFG_TEE_RAM_PH_SIZE - __init_end) >
+	ASSERT((TEE_RAM_VA_START + TEE_RAM_PH_SIZE - __init_end) >
 		SMALL_PAGE_SIZE, "Too few free pages to initialize paging")
 
 
 #endif /*CFG_WITH_PAGER*/
 
 #ifdef CFG_CORE_SANITIZE_KADDRESS
-	. = TEE_RAM_VA_START + (CFG_TEE_RAM_VA_SIZE * 8) / 9 - 8;
+	. = TEE_RAM_VA_START + (TEE_RAM_VA_SIZE * 8) / 9 - 8;
 	. = ALIGN(8);
 	.asan_shadow : {
 		__asan_shadow_start = .;
-		. += CFG_TEE_RAM_VA_SIZE / 9;
+		. += TEE_RAM_VA_SIZE / 9;
 		__asan_shadow_end = .;
 		__asan_shadow_size = __asan_shadow_end - __asan_shadow_start;
 	}
@@ -438,9 +438,9 @@ SECTIONS
 	 * Guard against moving the location counter backwards in the assignment
 	 * below.
 	 */
-	ASSERT(. <= (TEE_RAM_VA_START + CFG_TEE_RAM_VA_SIZE),
-		"CFG_TEE_RAM_VA_SIZE is too small")
-	. = TEE_RAM_VA_START + CFG_TEE_RAM_VA_SIZE;
+	ASSERT(. <= (TEE_RAM_VA_START + TEE_RAM_VA_SIZE),
+		"TEE_RAM_VA_SIZE is too small")
+	. = TEE_RAM_VA_START + TEE_RAM_VA_SIZE;
 
 	_end_of_ram = .;
 
@@ -479,7 +479,7 @@ __vcore_unpg_rw_size = __flatmap_unpg_rw_size;
  * binary data after the firmware build sequence.
  */
 #define __FLATMAP_PAGER_TRAILING_SPACE	\
-	(CFG_TEE_RAM_START + CFG_TEE_RAM_PH_SIZE - \
+	(TEE_RAM_START + TEE_RAM_PH_SIZE - \
 		(__flatmap_init_ro_start + __flatmap_init_ro_size))
 
 /* Paged/init read-only memories */
diff --git a/core/arch/arm/kernel/thread.c b/core/arch/arm/kernel/thread.c
index cf8b8b76..4f9653db 100644
--- a/core/arch/arm/kernel/thread.c
+++ b/core/arch/arm/kernel/thread.c
@@ -1271,7 +1271,7 @@ void thread_get_user_kcode(struct mobj **mobj, size_t *offset,
 {
 	core_mmu_get_user_va_range(va, NULL);
 	*mobj = mobj_tee_ram;
-	*offset = thread_user_kcode_va - CFG_TEE_RAM_START;
+	*offset = thread_user_kcode_va - TEE_RAM_START;
 	*sz = thread_user_kcode_size;
 }
 #endif
@@ -1286,7 +1286,7 @@ void thread_get_user_kdata(struct mobj **mobj, size_t *offset,
 	core_mmu_get_user_va_range(&v, NULL);
 	*va = v + thread_user_kcode_size;
 	*mobj = mobj_tee_ram;
-	*offset = (vaddr_t)thread_user_kdata_page - CFG_TEE_RAM_START;
+	*offset = (vaddr_t)thread_user_kdata_page - TEE_RAM_START;
 	*sz = sizeof(thread_user_kdata_page);
 }
 #endif
diff --git a/core/arch/arm/mm/core_mmu.c b/core/arch/arm/mm/core_mmu.c
index c2b261b2..eb49a540 100644
--- a/core/arch/arm/mm/core_mmu.c
+++ b/core/arch/arm/mm/core_mmu.c
@@ -99,8 +99,8 @@ register_sdp_mem(TEE_SDP_TEST_MEM_BASE, TEE_SDP_TEST_MEM_SIZE);
 #endif
 
 #ifdef CFG_CORE_RWDATA_NOEXEC
-register_phys_mem_ul(MEM_AREA_TEE_RAM_RO, CFG_TEE_RAM_START,
-		     VCORE_UNPG_RX_PA - CFG_TEE_RAM_START);
+register_phys_mem_ul(MEM_AREA_TEE_RAM_RO, TEE_RAM_START,
+		     VCORE_UNPG_RX_PA - TEE_RAM_START);
 register_phys_mem_ul(MEM_AREA_TEE_RAM_RX, VCORE_UNPG_RX_PA, VCORE_UNPG_RX_SZ);
 register_phys_mem_ul(MEM_AREA_TEE_RAM_RO, VCORE_UNPG_RO_PA, VCORE_UNPG_RO_SZ);
 register_phys_mem_ul(MEM_AREA_TEE_RAM_RW, VCORE_UNPG_RW_PA, VCORE_UNPG_RW_SZ);
@@ -109,7 +109,7 @@ register_phys_mem_ul(MEM_AREA_TEE_RAM_RX, VCORE_INIT_RX_PA, VCORE_INIT_RX_SZ);
 register_phys_mem_ul(MEM_AREA_TEE_RAM_RO, VCORE_INIT_RO_PA, VCORE_INIT_RO_SZ);
 #endif /*CFG_WITH_PAGER*/
 #else /*!CFG_CORE_RWDATA_NOEXEC*/
-register_phys_mem(MEM_AREA_TEE_RAM, CFG_TEE_RAM_START, CFG_TEE_RAM_PH_SIZE);
+register_phys_mem(MEM_AREA_TEE_RAM, TEE_RAM_START, TEE_RAM_PH_SIZE);
 #endif /*!CFG_CORE_RWDATA_NOEXEC*/
 
 #if defined(CFG_CORE_SANITIZE_KADDRESS) && defined(CFG_WITH_PAGER)
@@ -760,7 +760,7 @@ static void dump_xlat_table(vaddr_t va __unused, int level __unused)
 static void add_pager_vaspace(struct tee_mmap_region *mmap, size_t num_elems,
 			      vaddr_t begin, vaddr_t *end, size_t *last)
 {
-	size_t size = CFG_TEE_RAM_VA_SIZE - (*end - begin);
+	size_t size = TEE_RAM_VA_SIZE - (*end - begin);
 	size_t n;
 	size_t pos = 0;
 
@@ -897,7 +897,7 @@ static void init_mem_map(struct tee_mmap_region *memory_map, size_t num_elems)
 		end = MAX(end, ROUNDUP(map->va + map->size, map->region_size));
 	}
 	assert(va >= TEE_RAM_VA_START);
-	assert(end <= TEE_RAM_VA_START + CFG_TEE_RAM_VA_SIZE);
+	assert(end <= TEE_RAM_VA_START + TEE_RAM_VA_SIZE);
 
 	add_pager_vaspace(memory_map, num_elems, va, &end, &last);
 
@@ -1043,8 +1043,8 @@ bool core_pbuf_is(uint32_t attr, paddr_t pbuf, size_t len)
 		return pbuf_is_inside(nsec_shared, pbuf, len) ||
 			pbuf_is_nsec_ddr(pbuf, len);
 	case CORE_MEM_TEE_RAM:
-		return core_is_buffer_inside(pbuf, len, CFG_TEE_RAM_START,
-							CFG_TEE_RAM_PH_SIZE);
+		return core_is_buffer_inside(pbuf, len, TEE_RAM_START,
+							TEE_RAM_PH_SIZE);
 	case CORE_MEM_TA_RAM:
 		return core_is_buffer_inside(pbuf, len, CFG_TA_RAM_START,
 							CFG_TA_RAM_SIZE);
diff --git a/core/arch/arm/mm/tee_pager.c b/core/arch/arm/mm/tee_pager.c
index da7c08a6..a1d3a387 100644
--- a/core/arch/arm/mm/tee_pager.c
+++ b/core/arch/arm/mm/tee_pager.c
@@ -187,7 +187,7 @@ void tee_pager_get_stats(struct tee_pager_stats *stats)
 #define TBL_SHIFT	SMALL_PAGE_SHIFT
 
 #define EFFECTIVE_VA_SIZE \
-	(ROUNDUP(TEE_RAM_VA_START + CFG_TEE_RAM_VA_SIZE, \
+	(ROUNDUP(TEE_RAM_VA_START + TEE_RAM_VA_SIZE, \
 		 CORE_MMU_PGDIR_SIZE) - \
 	 ROUNDDOWN(TEE_RAM_VA_START, CORE_MMU_PGDIR_SIZE))
 
@@ -291,7 +291,7 @@ void *tee_pager_phys_to_virt(paddr_t pa)
 	while (true) {
 		while (idx < TBL_NUM_ENTRIES) {
 			v = core_mmu_idx2va(&pager_tables[n].tbl_info, idx);
-			if (v >= (TEE_RAM_VA_START + CFG_TEE_RAM_VA_SIZE))
+			if (v >= (TEE_RAM_VA_START + TEE_RAM_VA_SIZE))
 				return NULL;
 
 			core_mmu_get_entry(&pager_tables[n].tbl_info,
diff --git a/core/arch/arm/plat-d02/platform_config.h b/core/arch/arm/plat-d02/platform_config.h
index 38892e30..1d57950f 100644
--- a/core/arch/arm/plat-d02/platform_config.h
+++ b/core/arch/arm/plat-d02/platform_config.h
@@ -40,7 +40,7 @@
  *  0x5180_0000                                  -
  *    TA RAM: 16 MiB                             |
  *  0x5080_0000                                  | TZDRAM
- *    TEE RAM: 4 MiB (CFG_TEE_RAM_VA_SIZE)       |
+ *    TEE RAM: 4 MiB (TEE_RAM_VA_SIZE)		 |
  *  0x5040_0000 [TZDRAM_BASE, CFG_TEE_LOAD_ADDR] -
  *    Shared memory: 4 MiB                       | SHMEM
  *  0x5000_0000                                  -
@@ -76,26 +76,26 @@
 #define TZDRAM_BASE		0x50460000
 #define TZDRAM_SIZE		(20096 * 1024)
 
-#define CFG_TEE_RAM_START	TZSRAM_BASE
-#define CFG_TEE_RAM_PH_SIZE	TZSRAM_SIZE
+#define TEE_RAM_START		TZSRAM_BASE
+#define TEE_RAM_PH_SIZE		TZSRAM_SIZE
 #define CFG_TA_RAM_START	ROUNDUP(TZDRAM_BASE, CORE_MMU_DEVICE_SIZE)
 #define CFG_TA_RAM_SIZE		ROUNDDOWN(TZDRAM_SIZE, CORE_MMU_DEVICE_SIZE)
 
-#define CFG_TEE_RAM_VA_SIZE	(2 * 1024 * 1024)
+#define TEE_RAM_VA_SIZE		(2 * 1024 * 1024)
 
 #else /* CFG_WITH_PAGER */
 
 #define TZDRAM_BASE		0x50400000
 #define TZDRAM_SIZE		(20 * 1024 * 1024)
 
-#define CFG_TEE_RAM_START	TZDRAM_BASE
-#define CFG_TEE_RAM_PH_SIZE	CFG_TEE_RAM_VA_SIZE
-#define CFG_TA_RAM_START	ROUNDUP((TZDRAM_BASE + CFG_TEE_RAM_VA_SIZE), \
+#define TEE_RAM_START		TZDRAM_BASE
+#define TEE_RAM_PH_SIZE		TEE_RAM_VA_SIZE
+#define CFG_TA_RAM_START	ROUNDUP((TZDRAM_BASE + TEE_RAM_VA_SIZE), \
 					CORE_MMU_DEVICE_SIZE)
-#define CFG_TA_RAM_SIZE		ROUNDDOWN((TZDRAM_SIZE - CFG_TEE_RAM_VA_SIZE),\
+#define CFG_TA_RAM_SIZE		ROUNDDOWN((TZDRAM_SIZE - TEE_RAM_VA_SIZE),\
 					  CORE_MMU_DEVICE_SIZE)
 
-#define CFG_TEE_RAM_VA_SIZE	(4 * 1024 * 1024)
+#define TEE_RAM_VA_SIZE		(4 * 1024 * 1024)
 
 #endif /* CFG_WITH_PAGER */
 
diff --git a/core/arch/arm/plat-hikey/platform_config.h b/core/arch/arm/plat-hikey/platform_config.h
index a845b1cc..0302a57a 100644
--- a/core/arch/arm/plat-hikey/platform_config.h
+++ b/core/arch/arm/plat-hikey/platform_config.h
@@ -63,7 +63,7 @@
  *  0x4000_0000                               -
  *    TA RAM: 14 MiB                          |
  *  0x3F20_0000                               | TZDRAM
- *    TEE RAM: 2 MiB (CFG_TEE_RAM_VA_SIZE)    |
+ *    TEE RAM: 2 MiB (TEE_RAM_VA_SIZE)	      |
  *  0x3F00_0000 [TZDRAM_BASE, BL32_LOAD_ADDR] -
  *    Shared memory: 2 MiB                    |
  *  0x3EE0_0000                               | DRAM0
@@ -147,25 +147,25 @@
 
 #define CFG_TEE_CORE_NB_CORE	8
 
-#define CFG_TEE_RAM_VA_SIZE	(2 * 1024 * 1024)
+#define TEE_RAM_VA_SIZE		(2 * 1024 * 1024)
 
 #define CFG_TEE_LOAD_ADDR	0x3F000000
 
 #ifdef CFG_WITH_PAGER
 
-#define CFG_TEE_RAM_START	TZSRAM_BASE
-#define CFG_TEE_RAM_PH_SIZE	TZSRAM_SIZE
+#define TEE_RAM_START		TZSRAM_BASE
+#define TEE_RAM_PH_SIZE		TZSRAM_SIZE
 #define CFG_TA_RAM_START	ROUNDUP(TZDRAM_BASE, CORE_MMU_DEVICE_SIZE)
 #define CFG_TA_RAM_SIZE		ROUNDDOWN(TZDRAM_SIZE, CORE_MMU_DEVICE_SIZE)
 
 #else /* CFG_WITH_PAGER */
 
-#define CFG_TEE_RAM_PH_SIZE	CFG_TEE_RAM_VA_SIZE
-#define CFG_TEE_RAM_START	TZDRAM_BASE
-#define CFG_TA_RAM_START	ROUNDUP((TZDRAM_BASE + CFG_TEE_RAM_VA_SIZE), \
+#define TEE_RAM_PH_SIZE		TEE_RAM_VA_SIZE
+#define TEE_RAM_START		TZDRAM_BASE
+#define CFG_TA_RAM_START	ROUNDUP((TZDRAM_BASE + TEE_RAM_VA_SIZE), \
 					CORE_MMU_DEVICE_SIZE)
 
-#define CFG_TA_RAM_SIZE		ROUNDDOWN((TZDRAM_SIZE - CFG_TEE_RAM_VA_SIZE),\
+#define CFG_TA_RAM_SIZE		ROUNDDOWN((TZDRAM_SIZE - TEE_RAM_VA_SIZE),\
 					  CORE_MMU_DEVICE_SIZE)
 
 #endif /* CFG_WITH_PAGER */
diff --git a/core/arch/arm/plat-imx/config/config_imx6sx.h b/core/arch/arm/plat-imx/config/config_imx6sx.h
index a8f63860..4568409a 100644
--- a/core/arch/arm/plat-imx/config/config_imx6sx.h
+++ b/core/arch/arm/plat-imx/config/config_imx6sx.h
@@ -26,7 +26,7 @@
 #define CFG_SHMEM_START		(TZDRAM_BASE + TZDRAM_SIZE)
 #define CFG_SHMEM_SIZE		0x200000
 
-#define CFG_TEE_RAM_VA_SIZE	(1024 * 1024)
+#define TEE_RAM_VA_SIZE		(1024 * 1024)
 
 /*
  * Everything is in TZDRAM.
@@ -36,15 +36,15 @@
  * |        | TA_RAM  |
  * +--------+---------+
  */
-#define CFG_TEE_RAM_PH_SIZE     CFG_TEE_RAM_VA_SIZE
-#define CFG_TEE_RAM_START	TZDRAM_BASE
-#define CFG_TA_RAM_START	ROUNDUP((TZDRAM_BASE + CFG_TEE_RAM_VA_SIZE), \
+#define TEE_RAM_PH_SIZE		TEE_RAM_VA_SIZE
+#define TEE_RAM_START		TZDRAM_BASE
+#define CFG_TA_RAM_START	ROUNDUP((TZDRAM_BASE + TEE_RAM_VA_SIZE), \
 					CORE_MMU_DEVICE_SIZE)
-#define CFG_TA_RAM_SIZE		ROUNDDOWN((TZDRAM_SIZE - CFG_TEE_RAM_VA_SIZE), \
+#define CFG_TA_RAM_SIZE		ROUNDDOWN((TZDRAM_SIZE - TEE_RAM_VA_SIZE), \
 					  CORE_MMU_DEVICE_SIZE)
 
 #ifndef CFG_TEE_LOAD_ADDR
-#define CFG_TEE_LOAD_ADDR	CFG_TEE_RAM_START
+#define CFG_TEE_LOAD_ADDR	TEE_RAM_START
 #endif
 
 #define CONSOLE_UART_BASE	(CFG_UART_BASE)
diff --git a/core/arch/arm/plat-imx/config/config_imx7.h b/core/arch/arm/plat-imx/config/config_imx7.h
index 5ee292dd..fb7b3be2 100644
--- a/core/arch/arm/plat-imx/config/config_imx7.h
+++ b/core/arch/arm/plat-imx/config/config_imx7.h
@@ -24,7 +24,7 @@
 #define CFG_SHMEM_START		(TZDRAM_BASE + TZDRAM_SIZE)
 #define CFG_SHMEM_SIZE		0x200000
 
-#define CFG_TEE_RAM_VA_SIZE	(1024 * 1024)
+#define TEE_RAM_VA_SIZE		(1024 * 1024)
 
 /*
  * Everything is in TZDRAM.
@@ -34,15 +34,15 @@
  * |        | TA_RAM  |
  * +--------+---------+
  */
-#define CFG_TEE_RAM_PH_SIZE     CFG_TEE_RAM_VA_SIZE
-#define CFG_TEE_RAM_START	TZDRAM_BASE
-#define CFG_TA_RAM_START	ROUNDUP((TZDRAM_BASE + CFG_TEE_RAM_VA_SIZE), \
+#define TEE_RAM_PH_SIZE		TEE_RAM_VA_SIZE
+#define TEE_RAM_START		TZDRAM_BASE
+#define CFG_TA_RAM_START	ROUNDUP((TZDRAM_BASE + TEE_RAM_VA_SIZE), \
 					CORE_MMU_DEVICE_SIZE)
-#define CFG_TA_RAM_SIZE		ROUNDDOWN((TZDRAM_SIZE - CFG_TEE_RAM_VA_SIZE), \
+#define CFG_TA_RAM_SIZE		ROUNDDOWN((TZDRAM_SIZE - TEE_RAM_VA_SIZE), \
 					  CORE_MMU_DEVICE_SIZE)
 
 #ifndef CFG_TEE_LOAD_ADDR
-#define CFG_TEE_LOAD_ADDR	CFG_TEE_RAM_START
+#define CFG_TEE_LOAD_ADDR	TEE_RAM_START
 #endif
 
 #define CONSOLE_UART_BASE	(CFG_UART_BASE)
diff --git a/core/arch/arm/plat-imx/platform_config.h b/core/arch/arm/plat-imx/platform_config.h
index 99c42049..e24ff4d2 100644
--- a/core/arch/arm/plat-imx/platform_config.h
+++ b/core/arch/arm/plat-imx/platform_config.h
@@ -86,15 +86,15 @@
  * |        | TA_RAM  |
  * +--------+---------+
  */
-#define CFG_TEE_RAM_VA_SIZE	(1024 * 1024)
-#define CFG_TEE_RAM_PH_SIZE	CFG_TEE_RAM_VA_SIZE
-#define CFG_TEE_RAM_START	TZDRAM_BASE
-#define CFG_TA_RAM_START	ROUNDUP((TZDRAM_BASE + CFG_TEE_RAM_VA_SIZE), \
+#define TEE_RAM_VA_SIZE		(1024 * 1024)
+#define TEE_RAM_PH_SIZE		TEE_RAM_VA_SIZE
+#define TEE_RAM_START		TZDRAM_BASE
+#define CFG_TA_RAM_START	ROUNDUP((TZDRAM_BASE + TEE_RAM_VA_SIZE), \
 					CORE_MMU_DEVICE_SIZE)
-#define CFG_TA_RAM_SIZE		ROUNDDOWN((TZDRAM_SIZE - CFG_TEE_RAM_VA_SIZE), \
+#define CFG_TA_RAM_SIZE		ROUNDDOWN((TZDRAM_SIZE - TEE_RAM_VA_SIZE), \
 					  CORE_MMU_DEVICE_SIZE)
 #ifndef CFG_TEE_LOAD_ADDR
-#define CFG_TEE_LOAD_ADDR	CFG_TEE_RAM_START
+#define CFG_TEE_LOAD_ADDR	TEE_RAM_START
 #endif
 
 
@@ -137,7 +137,7 @@
 #endif
 
 /* Common RAM and cache controller configuration */
-#define CFG_TEE_RAM_VA_SIZE		(1024 * 1024)
+#define TEE_RAM_VA_SIZE			(1024 * 1024)
 
 #define DDR_PHYS_START			DRAM0_BASE
 #define DDR_SIZE			DRAM0_SIZE
@@ -272,11 +272,11 @@
 #define CFG_DDR_TEETZ_RESERVED_SIZE	0x01F00000
 
 #define CFG_PUB_RAM_SIZE		(1 * 1024 * 1024)
-#define CFG_TEE_RAM_PH_SIZE		TZSRAM_SIZE
+#define TEE_RAM_PH_SIZE			TZSRAM_SIZE
 
 #define TZDRAM_BASE			(CFG_DDR_TEETZ_RESERVED_START)
 #define TZDRAM_SIZE			(CFG_DDR_TEETZ_RESERVED_SIZE - \
-				CFG_PUB_RAM_SIZE)
+					 CFG_PUB_RAM_SIZE)
 
 #define CFG_TA_RAM_START		TZDRAM_BASE
 #define CFG_TA_RAM_SIZE			TZDRAM_SIZE
@@ -304,17 +304,17 @@
 #define CFG_DDR_TEETZ_RESERVED_SIZE	0x02000000
 
 #define CFG_PUB_RAM_SIZE		(1 * 1024 * 1024)
-#define CFG_TEE_RAM_PH_SIZE		(1 * 1024 * 1024)
+#define TEE_RAM_PH_SIZE			(1 * 1024 * 1024)
 
 #define TZDRAM_BASE			(CFG_DDR_TEETZ_RESERVED_START)
 #define TZDRAM_SIZE			(CFG_DDR_TEETZ_RESERVED_SIZE - \
-				CFG_PUB_RAM_SIZE)
+					 CFG_PUB_RAM_SIZE)
 
 #define CFG_TA_RAM_START		(CFG_DDR_TEETZ_RESERVED_START + \
-				CFG_TEE_RAM_PH_SIZE)
+					 TEE_RAM_PH_SIZE)
 #define CFG_TA_RAM_SIZE			(CFG_DDR_TEETZ_RESERVED_SIZE - \
-				CFG_TEE_RAM_PH_SIZE - \
-				CFG_PUB_RAM_SIZE)
+					 TEE_RAM_PH_SIZE - \
+					 CFG_PUB_RAM_SIZE)
 
 #endif /* CFG_WITH_PAGER */
 
@@ -322,7 +322,7 @@
 					 TZDRAM_SIZE)
 #define CFG_SHMEM_SIZE			CFG_PUB_RAM_SIZE
 
-#define CFG_TEE_RAM_START		TZDRAM_BASE
+#define TEE_RAM_START			TZDRAM_BASE
 
 #ifndef CFG_TEE_LOAD_ADDR
 #define CFG_TEE_LOAD_ADDR		TZDRAM_BASE
diff --git a/core/arch/arm/plat-ls/platform_config.h b/core/arch/arm/plat-ls/platform_config.h
index fc700ba0..21a5c4eb 100644
--- a/core/arch/arm/plat-ls/platform_config.h
+++ b/core/arch/arm/plat-ls/platform_config.h
@@ -71,7 +71,7 @@
 #define DRAM0_SIZE			0x80000000
 #define CFG_DDR_TEETZ_RESERVED_START	0xFC000000
 #define CFG_DDR_TEETZ_RESERVED_SIZE	0x03F00000
-#define CFG_TEE_RAM_VA_SIZE		(1024 * 1024)
+#define TEE_RAM_VA_SIZE			(1024 * 1024)
 #define CFG_PUB_RAM_SIZE		(1024 * 1024)
 #define CFG_TEE_CORE_NB_CORE		2
 #endif
@@ -80,7 +80,7 @@
 #define DRAM0_SIZE			0x40000000
 #define CFG_DDR_TEETZ_RESERVED_START	0xBC000000
 #define CFG_DDR_TEETZ_RESERVED_SIZE	0x03F00000
-#define CFG_TEE_RAM_VA_SIZE		(1024 * 1024)
+#define TEE_RAM_VA_SIZE			(1024 * 1024)
 #define CFG_PUB_RAM_SIZE		(1024 * 1024)
 #define CFG_TEE_CORE_NB_CORE		2
 #endif
@@ -89,7 +89,7 @@
 #define DRAM0_SIZE			0x80000000
 #define CFG_DDR_TEETZ_RESERVED_START	0xFC000000
 #define CFG_DDR_TEETZ_RESERVED_SIZE	0x04000000
-#define CFG_TEE_RAM_VA_SIZE		(2 * 1024 * 1024)
+#define TEE_RAM_VA_SIZE			(2 * 1024 * 1024)
 #define CFG_PUB_RAM_SIZE		(2 * 1024 * 1024)
 #define CFG_TEE_CORE_NB_CORE		4
 #endif
@@ -98,7 +98,7 @@
 #define DRAM0_SIZE			0x40000000
 #define CFG_DDR_TEETZ_RESERVED_START	0xBC000000
 #define CFG_DDR_TEETZ_RESERVED_SIZE	0x04000000
-#define CFG_TEE_RAM_VA_SIZE		(2 * 1024 * 1024)
+#define TEE_RAM_VA_SIZE			(2 * 1024 * 1024)
 #define CFG_PUB_RAM_SIZE		(2 * 1024 * 1024)
 #define CFG_TEE_CORE_NB_CORE		1
 #endif
@@ -139,24 +139,23 @@
 #error "Invalid CFG_DDR_TEETZ_RESERVED_SIZE: at least 4MB expected"
 #endif
 
-/* Full GlobalPlatform test suite requires CFG_SHMEM_SIZE to be at least 2MB */
-#define CFG_TEE_RAM_PH_SIZE		CFG_TEE_RAM_VA_SIZE
+/* Full GlobalPlatform test suite requires TEE_SHMEM_SIZE to be at least 2MB */
+#define TEE_RAM_PH_SIZE			TEE_RAM_VA_SIZE
 #define CFG_TA_RAM_SIZE			(CFG_DDR_TEETZ_RESERVED_SIZE - \
-					 CFG_TEE_RAM_PH_SIZE - CFG_PUB_RAM_SIZE)
+					 TEE_RAM_PH_SIZE - CFG_PUB_RAM_SIZE)
 
 /* define the secure/unsecure memory areas */
 #define TZDRAM_BASE			(CFG_DDR_TEETZ_RESERVED_START)
-#define TZDRAM_SIZE			(CFG_TEE_RAM_PH_SIZE + CFG_TA_RAM_SIZE)
+#define TZDRAM_SIZE			(TEE_RAM_PH_SIZE + CFG_TA_RAM_SIZE)
 
 #define CFG_SHMEM_START			(TZDRAM_BASE + TZDRAM_SIZE)
 #define CFG_SHMEM_SIZE			 CFG_PUB_RAM_SIZE
 
 /* define the memory areas (TEE_RAM must start at reserved DDR start addr */
-#define CFG_TEE_RAM_START		TZDRAM_BASE
-#define CFG_TA_RAM_START		(CFG_TEE_RAM_START + \
-					 CFG_TEE_RAM_PH_SIZE)
+#define TEE_RAM_START			TZDRAM_BASE
+#define CFG_TA_RAM_START		(TEE_RAM_START + TEE_RAM_PH_SIZE)
 #ifndef CFG_TEE_LOAD_ADDR
-#define CFG_TEE_LOAD_ADDR		CFG_TEE_RAM_START
+#define CFG_TEE_LOAD_ADDR		TEE_RAM_START
 #endif
 
 #endif /*PLATFORM_CONFIG_H*/
diff --git a/core/arch/arm/plat-marvell/platform_config.h b/core/arch/arm/plat-marvell/platform_config.h
index 7e5ebd74..fd8a2468 100644
--- a/core/arch/arm/plat-marvell/platform_config.h
+++ b/core/arch/arm/plat-marvell/platform_config.h
@@ -124,10 +124,10 @@
 #error "Unknown platform flavor"
 #endif
 
-#define CFG_TEE_RAM_VA_SIZE	SIZE_4M
+#define TEE_RAM_VA_SIZE		SIZE_4M
 
 #ifndef CFG_TEE_LOAD_ADDR
-#define CFG_TEE_LOAD_ADDR	CFG_TEE_RAM_START
+#define CFG_TEE_LOAD_ADDR	TEE_RAM_START
 #endif
 
 /*
@@ -140,9 +140,9 @@
  * |        | SDP RAM | (test pool, optional)
  * +--------+---------+
  */
-#define CFG_TEE_RAM_PH_SIZE	CFG_TEE_RAM_VA_SIZE
-#define CFG_TEE_RAM_START	TZDRAM_BASE
-#define CFG_TA_RAM_START	ROUNDUP(TZDRAM_BASE + CFG_TEE_RAM_VA_SIZE, \
+#define TEE_RAM_PH_SIZE		TEE_RAM_VA_SIZE
+#define TEE_RAM_START		TZDRAM_BASE
+#define CFG_TA_RAM_START	ROUNDUP(TZDRAM_BASE + TEE_RAM_VA_SIZE, \
 					CORE_MMU_DEVICE_SIZE)
 
 #define CFG_TA_RAM_SIZE		ROUNDDOWN(TZDRAM_SIZE - \
diff --git a/core/arch/arm/plat-mediatek/platform_config.h b/core/arch/arm/plat-mediatek/platform_config.h
index d48105df..f2330de2 100644
--- a/core/arch/arm/plat-mediatek/platform_config.h
+++ b/core/arch/arm/plat-mediatek/platform_config.h
@@ -47,10 +47,10 @@
 #error "Unknown platform flavor"
 #endif
 
-#define CFG_TEE_RAM_VA_SIZE	(1024 * 1024)
+#define TEE_RAM_VA_SIZE		(1024 * 1024)
 
 #ifndef CFG_TEE_LOAD_ADDR
-#define CFG_TEE_LOAD_ADDR	CFG_TEE_RAM_START
+#define CFG_TEE_LOAD_ADDR	TEE_RAM_START
 #endif
 
 /*
@@ -61,11 +61,11 @@
  * |        | TA_RAM  |
  * +--------+---------+
  */
-#define CFG_TEE_RAM_PH_SIZE	CFG_TEE_RAM_VA_SIZE
-#define CFG_TEE_RAM_START	TZDRAM_BASE
-#define CFG_TA_RAM_START	ROUNDUP((TZDRAM_BASE + CFG_TEE_RAM_VA_SIZE), \
+#define TEE_RAM_PH_SIZE		TEE_RAM_VA_SIZE
+#define TEE_RAM_START		TZDRAM_BASE
+#define CFG_TA_RAM_START	ROUNDUP((TZDRAM_BASE + TEE_RAM_VA_SIZE), \
 					CORE_MMU_DEVICE_SIZE)
-#define CFG_TA_RAM_SIZE		ROUNDDOWN((TZDRAM_SIZE - CFG_TEE_RAM_VA_SIZE), \
+#define CFG_TA_RAM_SIZE		ROUNDDOWN((TZDRAM_SIZE - TEE_RAM_VA_SIZE), \
 					  CORE_MMU_DEVICE_SIZE)
 
 #ifdef CFG_WITH_LPAE
diff --git a/core/arch/arm/plat-poplar/platform_config.h b/core/arch/arm/plat-poplar/platform_config.h
index 078675dc..a661a78d 100644
--- a/core/arch/arm/plat-poplar/platform_config.h
+++ b/core/arch/arm/plat-poplar/platform_config.h
@@ -55,7 +55,7 @@
  *  0x0320_0000                                  -
  *
  * CFG_WITH_PAGER=n                              -
- *    TEE RAM: 2 MiB (CFG_TEE_RAM_VA_SIZE)       | TZDRAM
+ *    TEE RAM: 2 MiB (TEE_RAM_VA_SIZE)           | TZDRAM
  *  0x0300_0000 [TZDRAM_BASE, CFG_TEE_LOAD_ADDR] -
  *
  * CFG_WITH_PAGER=y
@@ -119,8 +119,8 @@
 #define TZDRAM_BASE		0x03200000
 #define TZDRAM_SIZE		(14 * 1024 * 1024)
 
-#define CFG_TEE_RAM_START	TZSRAM_BASE
-#define CFG_TEE_RAM_PH_SIZE	TZSRAM_SIZE
+#define TEE_RAM_START		TZSRAM_BASE
+#define TEE_RAM_PH_SIZE		TZSRAM_SIZE
 #define CFG_TA_RAM_START	ROUNDUP(TZDRAM_BASE, CORE_MMU_DEVICE_SIZE)
 #define CFG_TA_RAM_SIZE		ROUNDDOWN(TZDRAM_SIZE, CORE_MMU_DEVICE_SIZE)
 
@@ -129,12 +129,12 @@
 #define TZDRAM_BASE		0x03000000
 #define TZDRAM_SIZE		(16 * 1024 * 1024)
 
-#define CFG_TEE_RAM_START	TZDRAM_BASE
-#define CFG_TEE_RAM_PH_SIZE	CFG_TEE_RAM_VA_SIZE
-#define CFG_TA_RAM_START	ROUNDUP((TZDRAM_BASE + CFG_TEE_RAM_VA_SIZE), \
+#define TEE_RAM_START		TZDRAM_BASE
+#define TEE_RAM_PH_SIZE		TEE_RAM_VA_SIZE
+#define CFG_TA_RAM_START	ROUNDUP((TZDRAM_BASE + TEE_RAM_VA_SIZE), \
 					CORE_MMU_DEVICE_SIZE)
 
-#define CFG_TA_RAM_SIZE		ROUNDDOWN((TZDRAM_SIZE - CFG_TEE_RAM_VA_SIZE),\
+#define CFG_TA_RAM_SIZE		ROUNDDOWN((TZDRAM_SIZE - TEE_RAM_VA_SIZE),\
 					CORE_MMU_DEVICE_SIZE)
 
 #endif /* CFG_WITH_PAGER */
@@ -144,7 +144,7 @@
 
 #define CFG_TEE_CORE_NB_CORE	4
 
-#define CFG_TEE_RAM_VA_SIZE	(2 * 1024 * 1024)
+#define TEE_RAM_VA_SIZE		(2 * 1024 * 1024)
 
 #define CFG_TEE_LOAD_ADDR	0x03000000 /* BL32_BASE */
 
diff --git a/core/arch/arm/plat-rcar/platform_config.h b/core/arch/arm/plat-rcar/platform_config.h
index 4b0dfc2c..0b433570 100644
--- a/core/arch/arm/plat-rcar/platform_config.h
+++ b/core/arch/arm/plat-rcar/platform_config.h
@@ -72,10 +72,10 @@
 #define CFG_SHMEM_START		(TZDRAM_BASE + TZDRAM_SIZE)
 #define CFG_SHMEM_SIZE		0x100000
 
-#define CFG_TEE_RAM_VA_SIZE	(1024 * 1024)
+#define TEE_RAM_VA_SIZE		(1024 * 1024)
 
 #ifndef CFG_TEE_LOAD_ADDR
-#define CFG_TEE_LOAD_ADDR	CFG_TEE_RAM_START
+#define CFG_TEE_LOAD_ADDR	TEE_RAM_START
 #endif
 
 /*
@@ -86,12 +86,11 @@
  * |        | TA_RAM  |
  * +--------+---------+
  */
-#define CFG_TEE_RAM_PH_SIZE	CFG_TEE_RAM_VA_SIZE
-#define CFG_TEE_RAM_START	(TZDRAM_BASE + 0x00100000)
-#define CFG_TA_RAM_START	ROUNDUP((CFG_TEE_RAM_START + \
-					CFG_TEE_RAM_VA_SIZE), \
+#define TEE_RAM_PH_SIZE		TEE_RAM_VA_SIZE
+#define TEE_RAM_START		(TZDRAM_BASE + 0x00100000)
+#define CFG_TA_RAM_START	ROUNDUP((TEE_RAM_START + TEE_RAM_VA_SIZE), \
 					CORE_MMU_DEVICE_SIZE)
-#define CFG_TA_RAM_SIZE		ROUNDDOWN((TZDRAM_SIZE - CFG_TEE_RAM_VA_SIZE), \
+#define CFG_TA_RAM_SIZE		ROUNDDOWN((TZDRAM_SIZE - TEE_RAM_VA_SIZE), \
 					  CORE_MMU_DEVICE_SIZE)
 
 #endif /*PLATFORM_CONFIG_H*/
diff --git a/core/arch/arm/plat-rockchip/platform_config.h b/core/arch/arm/plat-rockchip/platform_config.h
index 4eb36865..4547a3d4 100644
--- a/core/arch/arm/plat-rockchip/platform_config.h
+++ b/core/arch/arm/plat-rockchip/platform_config.h
@@ -66,7 +66,7 @@
 
 /* Location of trusted dram */
 #define CFG_TZDRAM_RSV_START	0x68400000
-#define CFG_TEE_RAM_VA_SIZE	(1024 * 1024)
+#define TEE_RAM_VA_SIZE		(1024 * 1024)
 
 /*
  * Rockchip memory map
@@ -79,18 +79,18 @@
  * | SHMEM  |         |  1 MiB |
  * +---------------------------+
  */
-#define CFG_TEE_RAM_PH_SIZE	CFG_TEE_RAM_VA_SIZE
-#define CFG_TEE_RAM_START	CFG_TZDRAM_RSV_START
-#define CFG_TEE_RAM_SIZE	CFG_TEE_RAM_VA_SIZE
+#define TEE_RAM_PH_SIZE		TEE_RAM_VA_SIZE
+#define TEE_RAM_START		CFG_TZDRAM_RSV_START
+#define TEE_RAM_SIZE		TEE_RAM_VA_SIZE
 
-#define CFG_TA_RAM_START	(CFG_TEE_RAM_START + CFG_TEE_RAM_SIZE)
+#define CFG_TA_RAM_START	(TEE_RAM_START + TEE_RAM_SIZE)
 #define CFG_TA_RAM_SIZE		(1024 * 1024)
 #define CFG_SHMEM_START		(CFG_TA_RAM_START + CFG_TA_RAM_SIZE)
 #define CFG_SHMEM_SIZE		(1024 * 1024)
 
 /* Location of trusted dram */
 #define TZDRAM_BASE		CFG_TZDRAM_RSV_START
-#define TZDRAM_SIZE		(CFG_TEE_RAM_SIZE + CFG_TA_RAM_SIZE)
+#define TZDRAM_SIZE		(TEE_RAM_SIZE + CFG_TA_RAM_SIZE)
 
 #define CFG_TEE_LOAD_ADDR	CFG_TZDRAM_RSV_START
 
diff --git a/core/arch/arm/plat-rpi3/platform_config.h b/core/arch/arm/plat-rpi3/platform_config.h
index 61a8cb68..10ce2b1a 100644
--- a/core/arch/arm/plat-rpi3/platform_config.h
+++ b/core/arch/arm/plat-rpi3/platform_config.h
@@ -53,7 +53,7 @@
  *  0x0a00_0000
  *    TA RAM: 16 MiB                          |
  *  0x0842_0000                               | TZDRAM
- *    TEE RAM: 4 MiB (CFG_TEE_RAM_VA_SIZE)    |
+ *    TEE RAM: 4 MiB (TEE_RAM_VA_SIZE)	      |
  *  0x0840_0000 [ARM Trusted Firmware       ] -
  *  0x0840_0000 [TZDRAM_BASE, BL32_LOAD_ADDR] -
  *    Shared memory: 4 MiB                    |
@@ -75,14 +75,14 @@
 
 #define CFG_TEE_CORE_NB_CORE	4
 
-#define CFG_TEE_RAM_VA_SIZE	(4 * 1024 * 1024)
+#define TEE_RAM_VA_SIZE		(4 * 1024 * 1024)
 
 #define CFG_TEE_LOAD_ADDR	(TZDRAM_BASE + 0x20000)
 
-#define CFG_TEE_RAM_PH_SIZE	CFG_TEE_RAM_VA_SIZE
-#define CFG_TEE_RAM_START	TZDRAM_BASE
+#define TEE_RAM_PH_SIZE		TEE_RAM_VA_SIZE
+#define TEE_RAM_START		TZDRAM_BASE
 
-#define CFG_TA_RAM_START	ROUNDUP((TZDRAM_BASE + CFG_TEE_RAM_VA_SIZE), \
+#define CFG_TA_RAM_START	ROUNDUP((TZDRAM_BASE + TEE_RAM_VA_SIZE), \
 					CORE_MMU_DEVICE_SIZE)
 
 # define CFG_TA_RAM_SIZE        (16 * 1024 * 1024)
diff --git a/core/arch/arm/plat-sam/platform_config.h b/core/arch/arm/plat-sam/platform_config.h
index 6bdc70f5..fb743956 100644
--- a/core/arch/arm/plat-sam/platform_config.h
+++ b/core/arch/arm/plat-sam/platform_config.h
@@ -52,7 +52,7 @@
  * |        | TA_RAM 7MiB  |
  * + TZDRAM +--------------+ 0x3010_0000 [CFG_TA_RAM_START]
  * |        | TEE_RAM 1MiB |
- * +-----------------------+ 0x3000_0000 [CFG_TEE_RAM_START/LOAD_ADDR]
+ * +-----------------------+ 0x3000_0000 [TEE_RAM_START/CFG_TEE_LOAD_ADDR]
  * |      Linux memory     |
  * +-----------------------+ 0x2000_0000 [DRAM0_BASE]
  */
@@ -63,18 +63,18 @@
 #define CFG_SHMEM_START     (TZDRAM_BASE + TZDRAM_SIZE)
 #define CFG_SHMEM_SIZE      (4 * 1024 * 1024)
 
-#define CFG_TEE_RAM_START   TZDRAM_BASE
-#define CFG_TEE_RAM_VA_SIZE (1 * 1024 * 1024)
-#define CFG_TEE_RAM_PH_SIZE CFG_TEE_RAM_VA_SIZE
+#define TEE_RAM_START		TZDRAM_BASE
+#define TEE_RAM_VA_SIZE		(1 * 1024 * 1024)
+#define TEE_RAM_PH_SIZE		TEE_RAM_VA_SIZE
 
 #ifndef CFG_TEE_LOAD_ADDR
-#define CFG_TEE_LOAD_ADDR   CFG_TEE_RAM_START
+#define CFG_TEE_LOAD_ADDR	TEE_RAM_START
 #endif
 
-#define CFG_TA_RAM_START    ROUNDUP((TZDRAM_BASE + CFG_TEE_RAM_VA_SIZE), \
-				     CORE_MMU_DEVICE_SIZE)
-#define CFG_TA_RAM_SIZE     ROUNDDOWN((TZDRAM_SIZE - CFG_TEE_RAM_VA_SIZE), \
-				     CORE_MMU_DEVICE_SIZE)
+#define CFG_TA_RAM_START	ROUNDUP((TZDRAM_BASE + TEE_RAM_VA_SIZE), \
+					CORE_MMU_DEVICE_SIZE)
+#define CFG_TA_RAM_SIZE		ROUNDDOWN((TZDRAM_SIZE - TEE_RAM_VA_SIZE), \
+					CORE_MMU_DEVICE_SIZE)
 
 #define PL310_BASE          (AT91C_BASE_L2CC)
 #define SFR_BASE            (AT91C_BASE_SFR)
diff --git a/core/arch/arm/plat-sprd/platform_config.h b/core/arch/arm/plat-sprd/platform_config.h
index 4c530ef6..95d5d6e5 100644
--- a/core/arch/arm/plat-sprd/platform_config.h
+++ b/core/arch/arm/plat-sprd/platform_config.h
@@ -66,10 +66,10 @@
 #error "Unknown platform flavor"
 #endif
 
-#define CFG_TEE_RAM_VA_SIZE	(1024 * 1024)
+#define TEE_RAM_VA_SIZE		(1024 * 1024)
 
 #ifndef CFG_TEE_LOAD_ADDR
-#define CFG_TEE_LOAD_ADDR	CFG_TEE_RAM_START
+#define CFG_TEE_LOAD_ADDR	TEE_RAM_START
 #endif
 
 /*
@@ -79,11 +79,11 @@
  * |        | TA_RAM  |
  * +--------+---------+
  */
-#define CFG_TEE_RAM_PH_SIZE	CFG_TEE_RAM_VA_SIZE
-#define CFG_TEE_RAM_START	TZDRAM_BASE
-#define CFG_TA_RAM_START	ROUNDUP((TZDRAM_BASE + CFG_TEE_RAM_VA_SIZE), \
+#define TEE_RAM_PH_SIZE		TEE_RAM_VA_SIZE
+#define TEE_RAM_START		TZDRAM_BASE
+#define CFG_TA_RAM_START	ROUNDUP((TZDRAM_BASE + TEE_RAM_VA_SIZE), \
 					CORE_MMU_DEVICE_SIZE)
-#define CFG_TA_RAM_SIZE		ROUNDDOWN((TZDRAM_SIZE - CFG_TEE_RAM_VA_SIZE), \
+#define CFG_TA_RAM_SIZE		ROUNDDOWN((TZDRAM_SIZE - TEE_RAM_VA_SIZE), \
 					  CORE_MMU_DEVICE_SIZE)
 
 #endif /*PLATFORM_CONFIG_H*/
diff --git a/core/arch/arm/plat-stm/platform_config.h b/core/arch/arm/plat-stm/platform_config.h
index d7a08cde..6be78097 100644
--- a/core/arch/arm/plat-stm/platform_config.h
+++ b/core/arch/arm/plat-stm/platform_config.h
@@ -304,8 +304,8 @@
 				CFG_SHMEM_SIZE - \
 					TEE_SDP_TEST_MEM_SIZE)
 
-#define CFG_TEE_RAM_START	TZSRAM_BASE
-#define CFG_TEE_RAM_PH_SIZE	TZSRAM_SIZE
+#define TEE_RAM_START		TZSRAM_BASE
+#define TEE_RAM_PH_SIZE		TZSRAM_SIZE
 
 #define CFG_TA_RAM_START	TZDRAM_BASE
 #define CFG_TA_RAM_SIZE		TZDRAM_SIZE
@@ -317,22 +317,18 @@
 				CFG_SHMEM_SIZE - \
 					TEE_SDP_TEST_MEM_SIZE)
 
-#define CFG_TEE_RAM_START	TZDRAM_BASE
-#ifndef CFG_TEE_RAM_PH_SIZE
-#define CFG_TEE_RAM_PH_SIZE	(1 * 1024 * 1024)
-#endif
+#define TEE_RAM_START		TZDRAM_BASE
+#define TEE_RAM_PH_SIZE		(1 * 1024 * 1024)
 
-#define CFG_TA_RAM_START	(TZDRAM_BASE + CFG_TEE_RAM_PH_SIZE)
-#define CFG_TA_RAM_SIZE		(TZDRAM_SIZE - CFG_TEE_RAM_PH_SIZE)
+#define CFG_TA_RAM_START	(TZDRAM_BASE + TEE_RAM_PH_SIZE)
+#define CFG_TA_RAM_SIZE		(TZDRAM_SIZE - TEE_RAM_PH_SIZE)
 
 #endif /* !CFG_WITH_PAGER */
 
-#ifndef CFG_TEE_RAM_VA_SIZE
-#define CFG_TEE_RAM_VA_SIZE	(1024 * 1024)
-#endif
+#define TEE_RAM_VA_SIZE		(1024 * 1024)
 
 #ifndef CFG_TEE_LOAD_ADDR
-#define CFG_TEE_LOAD_ADDR	CFG_TEE_RAM_START
+#define CFG_TEE_LOAD_ADDR	TEE_RAM_START
 #endif
 
 #define PL310_BASE		(CPU_IOMEM_BASE + 0x2000)
diff --git a/core/arch/arm/plat-ti/main.c b/core/arch/arm/plat-ti/main.c
index 68e07a6f..4b51e58a 100644
--- a/core/arch/arm/plat-ti/main.c
+++ b/core/arch/arm/plat-ti/main.c
@@ -32,7 +32,7 @@ static struct gic_data gic_data;
 static struct serial8250_uart_data console_data;
 static uint8_t plat_huk[PLAT_HW_UNIQUE_KEY_LENGTH];
 
-register_phys_mem(MEM_AREA_RAM_SEC, TZDRAM_BASE, CFG_TEE_RAM_VA_SIZE);
+register_phys_mem(MEM_AREA_RAM_SEC, TZDRAM_BASE, TEE_RAM_VA_SIZE);
 register_phys_mem(MEM_AREA_IO_SEC, SECRAM_BASE, SECRAM_SIZE);
 register_phys_mem(MEM_AREA_IO_SEC, GICC_BASE, GICC_SIZE);
 register_phys_mem(MEM_AREA_IO_SEC, GICD_BASE, GICD_SIZE);
diff --git a/core/arch/arm/plat-ti/platform_config.h b/core/arch/arm/plat-ti/platform_config.h
index 95e3fbca..f0b4e146 100644
--- a/core/arch/arm/plat-ti/platform_config.h
+++ b/core/arch/arm/plat-ti/platform_config.h
@@ -107,10 +107,10 @@
  * | TZSRAM | TEE_RAM  |
  * +--------+----------+
  */
-#define CFG_TEE_RAM_VA_SIZE     (1 * 1024 * 1024)
-#define CFG_TEE_RAM_PH_SIZE     TZSRAM_SIZE
-#define CFG_TEE_RAM_START       TZSRAM_BASE
-#define CFG_TEE_LOAD_ADDR       (CFG_TEE_RAM_START + 0x1000)
+#define TEE_RAM_VA_SIZE		(1 * 1024 * 1024)
+#define TEE_RAM_PH_SIZE		TZSRAM_SIZE
+#define TEE_RAM_START		TZSRAM_BASE
+#define CFG_TEE_LOAD_ADDR	(TEE_RAM_START + 0x1000)
 
 #else /* CFG_WITH_PAGER */
 /*
@@ -124,10 +124,10 @@
  * |        | TEE_RAM |
  * +--------+---------+
  */
-#define CFG_TEE_RAM_VA_SIZE     (1 * 1024 * 1024)
-#define CFG_TEE_RAM_PH_SIZE     CFG_TEE_RAM_VA_SIZE
-#define CFG_TEE_RAM_START       TZDRAM_BASE
-#define CFG_TEE_LOAD_ADDR       CFG_TEE_RAM_START
+#define TEE_RAM_VA_SIZE		(1 * 1024 * 1024)
+#define TEE_RAM_PH_SIZE		TEE_RAM_VA_SIZE
+#define TEE_RAM_START		TZDRAM_BASE
+#define CFG_TEE_LOAD_ADDR	TEE_RAM_START
 
 #endif /* CFG_WITH_PAGER */
 
@@ -140,11 +140,10 @@
 #define TEE_SDP_TEST_MEM_SIZE	0
 #endif /*CFG_SECURE_DATA_PATH*/
 
-#define CFG_TA_RAM_START	ROUNDUP((TZDRAM_BASE + CFG_TEE_RAM_VA_SIZE), \
+#define CFG_TA_RAM_START	ROUNDUP((TZDRAM_BASE + TEE_RAM_VA_SIZE), \
 					CORE_MMU_DEVICE_SIZE)
 
-#define TA_RAM_SIZE		ROUNDDOWN((TZDRAM_SIZE - \
-						CFG_TEE_RAM_VA_SIZE) - \
+#define CFG_TA_RAM_SIZE		ROUNDDOWN((TZDRAM_SIZE - TEE_RAM_VA_SIZE) - \
 						TEE_SDP_TEST_MEM_SIZE, \
 					   CORE_MMU_DEVICE_SIZE)
 
diff --git a/core/arch/arm/plat-vexpress/platform_config.h b/core/arch/arm/plat-vexpress/platform_config.h
index fd42f770..77aaf6de 100644
--- a/core/arch/arm/plat-vexpress/platform_config.h
+++ b/core/arch/arm/plat-vexpress/platform_config.h
@@ -95,8 +95,8 @@
 #define TZSRAM_BASE		(0x06000000)
 #define TZSRAM_SIZE		CFG_CORE_TZSRAM_EMUL_SIZE
 
-#define TZDRAM_BASE		(TZSRAM_BASE + CFG_TEE_RAM_VA_SIZE)
-#define TZDRAM_SIZE		(0x02000000 - CFG_TEE_RAM_VA_SIZE)
+#define TZDRAM_BASE		(TZSRAM_BASE + TEE_RAM_VA_SIZE)
+#define TZDRAM_SIZE		(0x02000000 - TEE_RAM_VA_SIZE)
 
 #else /*CFG_WITH_PAGER*/
 
@@ -131,8 +131,8 @@
 #define TZSRAM_BASE		0xFF000000
 #define TZSRAM_SIZE		CFG_CORE_TZSRAM_EMUL_SIZE
 
-#define TZDRAM_BASE		(TZSRAM_BASE + CFG_TEE_RAM_VA_SIZE)
-#define TZDRAM_SIZE		(0x00E00000 - CFG_TEE_RAM_VA_SIZE)
+#define TZDRAM_BASE		(TZSRAM_BASE + TEE_RAM_VA_SIZE)
+#define TZDRAM_SIZE		(0x00E00000 - TEE_RAM_VA_SIZE)
 
 #else /*CFG_WITH_PAGER*/
 /*
@@ -179,8 +179,8 @@
 #define TZSRAM_BASE		(SECRAM_BASE + 0x00100000)
 #define TZSRAM_SIZE		CFG_CORE_TZSRAM_EMUL_SIZE
 
-#define TZDRAM_BASE		(TZSRAM_BASE + CFG_TEE_RAM_VA_SIZE)
-#define TZDRAM_SIZE		(SECRAM_SIZE - CFG_TEE_RAM_VA_SIZE - \
+#define TZDRAM_BASE		(TZSRAM_BASE + TEE_RAM_VA_SIZE)
+#define TZDRAM_SIZE		(SECRAM_SIZE - TEE_RAM_VA_SIZE - \
 					TZSRAM_SIZE - 0x00100000)
 
 #else /* CFG_WITH_PAGER */
@@ -240,10 +240,10 @@
 #error "Unknown platform flavor"
 #endif
 
-#define CFG_TEE_RAM_VA_SIZE	(2 * 1024 * 1024)
+#define TEE_RAM_VA_SIZE		(2 * 1024 * 1024)
 
 #ifndef CFG_TEE_LOAD_ADDR
-#define CFG_TEE_LOAD_ADDR	CFG_TEE_RAM_START
+#define CFG_TEE_LOAD_ADDR	TEE_RAM_START
 #endif
 
 #ifdef CFG_WITH_PAGER
@@ -259,8 +259,8 @@
  * |        | SDP RAM | (SDP test pool, optional)
  * +--------+---------+
  */
-#define CFG_TEE_RAM_PH_SIZE	TZSRAM_SIZE
-#define CFG_TEE_RAM_START	TZSRAM_BASE
+#define TEE_RAM_PH_SIZE		TZSRAM_SIZE
+#define TEE_RAM_START		TZSRAM_BASE
 #define CFG_TA_RAM_START	ROUNDUP(TZDRAM_BASE, CORE_MMU_DEVICE_SIZE)
 
 #else
@@ -275,9 +275,9 @@
  * |        | SDP RAM | (test pool, optional)
  * +--------+---------+
  */
-#define CFG_TEE_RAM_PH_SIZE	CFG_TEE_RAM_VA_SIZE
-#define CFG_TEE_RAM_START	TZDRAM_BASE
-#define CFG_TA_RAM_START	ROUNDUP(TZDRAM_BASE + CFG_TEE_RAM_VA_SIZE, \
+#define TEE_RAM_PH_SIZE		TEE_RAM_VA_SIZE
+#define TEE_RAM_START		TZDRAM_BASE
+#define CFG_TA_RAM_START	ROUNDUP(TZDRAM_BASE + TEE_RAM_VA_SIZE, \
 					CORE_MMU_DEVICE_SIZE)
 #endif
 
diff --git a/core/arch/arm/plat-zynq7k/platform_config.h b/core/arch/arm/plat-zynq7k/platform_config.h
index 6c006569..bd4ad2ff 100644
--- a/core/arch/arm/plat-zynq7k/platform_config.h
+++ b/core/arch/arm/plat-zynq7k/platform_config.h
@@ -69,7 +69,7 @@
 #define DRAM0_BASE			0x00100000
 #define DRAM0_SIZE			0x3FF00000
 
-#define CFG_TEE_RAM_VA_SIZE		(1024 * 1024)
+#define TEE_RAM_VA_SIZE			(1024 * 1024)
 
 #define CFG_TEE_CORE_NB_CORE		2
 
@@ -208,7 +208,7 @@
 #define CFG_DDR_TEETZ_RESERVED_SIZE	0x01F00000
 
 #define CFG_PUB_RAM_SIZE		(1 * 1024 * 1024)
-#define CFG_TEE_RAM_PH_SIZE		TZSRAM_SIZE
+#define TEE_RAM_PH_SIZE			TZSRAM_SIZE
 
 #define TZDRAM_BASE			(CFG_DDR_TEETZ_RESERVED_START)
 #define TZDRAM_SIZE				(CFG_DDR_TEETZ_RESERVED_SIZE - \
@@ -221,7 +221,7 @@
 #define CFG_TA_RAM_START		TZDRAM_BASE
 #define CFG_TA_RAM_SIZE			TZDRAM_SIZE
 
-#define CFG_TEE_RAM_START		TZSRAM_BASE
+#define TEE_RAM_START			TZSRAM_BASE
 
 #ifndef CFG_TEE_LOAD_ADDR
 #define CFG_TEE_LOAD_ADDR		TZSRAM_BASE
@@ -250,23 +250,23 @@
 #define CFG_DDR_TEETZ_RESERVED_SIZE	0x02000000
 
 #define CFG_PUB_RAM_SIZE		(1 * 1024 * 1024)
-#define CFG_TEE_RAM_PH_SIZE		(1 * 1024 * 1024)
+#define TEE_RAM_PH_SIZE		(1 * 1024 * 1024)
 
 #define TZDRAM_BASE			(CFG_DDR_TEETZ_RESERVED_START)
 #define TZDRAM_SIZE			(CFG_DDR_TEETZ_RESERVED_SIZE - \
 						CFG_PUB_RAM_SIZE)
 
 #define CFG_TA_RAM_START		(CFG_DDR_TEETZ_RESERVED_START + \
-						CFG_TEE_RAM_PH_SIZE)
+						TEE_RAM_PH_SIZE)
 #define CFG_TA_RAM_SIZE			(CFG_DDR_TEETZ_RESERVED_SIZE - \
-						CFG_TEE_RAM_PH_SIZE - \
+						TEE_RAM_PH_SIZE - \
 						CFG_PUB_RAM_SIZE)
 
 #define CFG_SHMEM_START			(CFG_DDR_TEETZ_RESERVED_START + \
 						TZDRAM_SIZE)
 #define CFG_SHMEM_SIZE			CFG_PUB_RAM_SIZE
 
-#define CFG_TEE_RAM_START		TZDRAM_BASE
+#define TEE_RAM_START			TZDRAM_BASE
 
 #ifndef CFG_TEE_LOAD_ADDR
 #define CFG_TEE_LOAD_ADDR		TZDRAM_BASE
diff --git a/core/arch/arm/plat-zynqmp/platform_config.h b/core/arch/arm/plat-zynqmp/platform_config.h
index 12975808..10155d8b 100644
--- a/core/arch/arm/plat-zynqmp/platform_config.h
+++ b/core/arch/arm/plat-zynqmp/platform_config.h
@@ -72,10 +72,10 @@
 
 #define CFG_TEE_CORE_NB_CORE	4
 
-#define CFG_TEE_RAM_VA_SIZE	(1024 * 1024)
+#define TEE_RAM_VA_SIZE		(1024 * 1024)
 
 #ifndef CFG_TEE_LOAD_ADDR
-#define CFG_TEE_LOAD_ADDR	CFG_TEE_RAM_START
+#define CFG_TEE_LOAD_ADDR	TEE_RAM_START
 #endif
 
 /*
@@ -87,11 +87,11 @@
  * |        | TA_RAM  |
  * +--------+---------+
  */
-#define CFG_TEE_RAM_PH_SIZE	CFG_TEE_RAM_VA_SIZE
-#define CFG_TEE_RAM_START	TZDRAM_BASE
-#define CFG_TA_RAM_START	ROUNDUP((TZDRAM_BASE + CFG_TEE_RAM_VA_SIZE), \
+#define TEE_RAM_PH_SIZE		TEE_RAM_VA_SIZE
+#define TEE_RAM_START		TZDRAM_BASE
+#define CFG_TA_RAM_START	ROUNDUP((TZDRAM_BASE + TEE_RAM_VA_SIZE), \
 					CORE_MMU_DEVICE_SIZE)
-#define CFG_TA_RAM_SIZE		ROUNDDOWN((TZDRAM_SIZE - CFG_TEE_RAM_VA_SIZE), \
+#define CFG_TA_RAM_SIZE		ROUNDDOWN((TZDRAM_SIZE - TEE_RAM_VA_SIZE), \
 					  CORE_MMU_DEVICE_SIZE)
 
 #ifndef UART_BAUDRATE
diff --git a/core/arch/arm/tee/entry_std.c b/core/arch/arm/tee/entry_std.c
index d256b276..c6d0ea89 100644
--- a/core/arch/arm/tee/entry_std.c
+++ b/core/arch/arm/tee/entry_std.c
@@ -594,9 +594,9 @@ static TEE_Result default_mobj_init(void)
 	if (!mobj_sec_ddr)
 		panic("Failed to register secure ta ram");
 
-	mobj_tee_ram = mobj_phys_alloc(CFG_TEE_RAM_START,
+	mobj_tee_ram = mobj_phys_alloc(TEE_RAM_START,
 				       VCORE_UNPG_RW_PA + VCORE_UNPG_RW_SZ -
-						CFG_TEE_RAM_START,
+						TEE_RAM_START,
 				       TEE_MATTR_CACHE_CACHED,
 				       CORE_MEM_TEE_RAM);
 	if (!mobj_tee_ram)
diff --git a/documentation/porting_guidelines.md b/documentation/porting_guidelines.md
index 27710bb0..6cb7880d 100644
--- a/documentation/porting_guidelines.md
+++ b/documentation/porting_guidelines.md
@@ -160,12 +160,12 @@ could look like this:
 
 #define CFG_TEE_CORE_NB_CORE	4
 
-#define CFG_TEE_RAM_VA_SIZE	(4 * 1024 * 1024)
+#define TEE_RAM_VA_SIZE	(4 * 1024 * 1024)
 
 #define CFG_TEE_LOAD_ADDR	(TZDRAM_BASE + 0x20000)
 
-#define CFG_TEE_RAM_PH_SIZE	CFG_TEE_RAM_VA_SIZE
-#define CFG_TEE_RAM_START	TZDRAM_BASE
+#define TEE_RAM_PH_SIZE		TEE_RAM_VA_SIZE
+#define TEE_RAM_START		TZDRAM_BASE
 
 #define CFG_TA_RAM_START	ROUNDUP((TZDRAM_BASE + CFG_TEE_RAM_VA_SIZE), \
 					CORE_MMU_DEVICE_SIZE)
author	Etienne Carriere <etienne.carriere@linaro.org>	2018-04-25 15:24:25 +0200
committer	Jérôme Forissier <jerome.forissier@linaro.org>	2018-04-25 18:26:18 +0200
commit	446cc62a848e343a9d08e23476ba102fbc02065f (patch)
tree	d9a032b883659553255e229dfa2ee17c57c3d196
parent	847b6aa6bb4abda37ec00c23cc2b53564c02ed29 (diff)