diff options
| author | Achin Gupta <achin.gupta@arm.com> | 2014-05-09 12:00:17 +0100 |
|---|---|---|
| committer | Achin Gupta <achin.gupta@arm.com> | 2014-05-22 17:47:20 +0100 |
| commit | fa9c08b7d117cb736911288668f9fd987505b4e3 (patch) | |
| tree | c935c5a3ab474265b51c2b1c8c53ec798e9fee2c /services | |
| parent | dce74b891e0e6020d0a18384e32f280133631d9b (diff) | |
Use secure timer to generate S-EL1 interrupts
This patch adds support in the TSP to program the secure physical
generic timer to generate a EL-1 interrupt every half second. It also
adds support for maintaining the timer state across power management
operations. The TSPD ensures that S-EL1 can access the timer by
programming the SCR_EL3.ST bit.
This patch does not actually enable the timer. This will be done in a
subsequent patch once the complete framework for handling S-EL1
interrupts is in place.
Change-Id: I1b3985cfb50262f60824be3a51c6314ce90571bc
Diffstat (limited to 'services')
| -rw-r--r-- | services/spd/tspd/tspd_common.c | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/services/spd/tspd/tspd_common.c b/services/spd/tspd/tspd_common.c index 2d0b08b..d975ec4 100644 --- a/services/spd/tspd/tspd_common.c +++ b/services/spd/tspd/tspd_common.c @@ -65,10 +65,14 @@ int32_t tspd_init_secure_context(uint64_t entrypoint, */ memset(tsp_ctx, 0, sizeof(*tsp_ctx)); - /* Set the right security state and register width for the SP */ + /* + * Set the right security state, register width and enable access to + * the secure physical timer for the SP. + */ scr = read_scr(); scr &= ~SCR_NS_BIT; scr &= ~SCR_RW_BIT; + scr |= SCR_ST_BIT; if (rw == TSP_AARCH64) scr |= SCR_RW_BIT; |