Merge pull request #152 from jcastillo-arm/jc/tf-issues/073-v2

Remove all checkpatch errors from codebase

6 files changed, 12 insertions, 12 deletions

diff --git a/plat/common/aarch64/plat_common.c b/plat/common/aarch64/plat_common.c
index 2abf29d..94b9dfd 100644
--- a/plat/common/aarch64/plat_common.c
+++ b/plat/common/aarch64/plat_common.c
@@ -38,12 +38,12 @@
 #pragma weak bl31_plat_enable_mmu
 #pragma weak bl32_plat_enable_mmu
 
-void bl31_plat_enable_mmu()
+void bl31_plat_enable_mmu(void)
 {
 	enable_mmu_el3();
 }
 
-void bl32_plat_enable_mmu()
+void bl32_plat_enable_mmu(void)
 {
 	enable_mmu_el1();
 }
diff --git a/plat/fvp/bl2_fvp_setup.c b/plat/fvp/bl2_fvp_setup.c
index de9c6a4..a030bd5 100644
--- a/plat/fvp/bl2_fvp_setup.c
+++ b/plat/fvp/bl2_fvp_setup.c
@@ -212,7 +212,7 @@ void bl2_plat_flush_bl31_params(void)
  * Perform the very early platform specific architectural setup here. At the
  * moment this is only intializes the mmu in a quick and dirty way.
  ******************************************************************************/
-void bl2_plat_arch_setup()
+void bl2_plat_arch_setup(void)
 {
 	fvp_configure_mmu_el1(bl2_tzram_layout.total_base,
 			      bl2_tzram_layout.total_size,
diff --git a/plat/fvp/bl31_fvp_setup.c b/plat/fvp/bl31_fvp_setup.c
index 6554ec3..50ed0b0 100644
--- a/plat/fvp/bl31_fvp_setup.c
+++ b/plat/fvp/bl31_fvp_setup.c
@@ -167,7 +167,7 @@ void bl31_early_platform_setup(bl31_params_t *from_bl2,
  * Initialize the gic, configure the CLCD and zero out variables needed by the
  * secondaries to boot up correctly.
  ******************************************************************************/
-void bl31_platform_setup()
+void bl31_platform_setup(void)
 {
 	unsigned int reg_val;
 
@@ -207,7 +207,7 @@ void bl31_platform_setup()
  * Perform the very early platform specific architectural setup here. At the
  * moment this is only intializes the mmu in a quick and dirty way.
  ******************************************************************************/
-void bl31_plat_arch_setup()
+void bl31_plat_arch_setup(void)
 {
 #if RESET_TO_BL31
 	fvp_cci_setup();
diff --git a/plat/fvp/bl32_fvp_setup.c b/plat/fvp/bl32_fvp_setup.c
index f8dc3c7..3c09ca2 100644
--- a/plat/fvp/bl32_fvp_setup.c
+++ b/plat/fvp/bl32_fvp_setup.c
@@ -81,7 +81,7 @@ void bl32_early_platform_setup(void)
 /*******************************************************************************
  * Perform platform specific setup placeholder
  ******************************************************************************/
-void bl32_platform_setup()
+void bl32_platform_setup(void)
 {
 
 }
@@ -90,7 +90,7 @@ void bl32_platform_setup()
  * Perform the very early platform specific architectural setup here. At the
  * moment this is only intializes the MMU
  ******************************************************************************/
-void bl32_plat_arch_setup()
+void bl32_plat_arch_setup(void)
 {
 	fvp_configure_mmu_el1(BL32_RO_BASE,
 			      (BL32_COHERENT_RAM_LIMIT - BL32_RO_BASE),
diff --git a/plat/fvp/fvp_gic.c b/plat/fvp/fvp_gic.c
index 3156da9..a48b29b 100644
--- a/plat/fvp/fvp_gic.c
+++ b/plat/fvp/fvp_gic.c
@@ -324,7 +324,7 @@ uint32_t plat_interrupt_type_to_line(uint32_t type, uint32_t security_state)
  * the GIC cpu interface. INTR_TYPE_INVAL is returned when there is no
  * interrupt pending.
  ******************************************************************************/
-uint32_t plat_ic_get_pending_interrupt_type()
+uint32_t plat_ic_get_pending_interrupt_type(void)
 {
 	uint32_t id, gicc_base;
 
@@ -346,7 +346,7 @@ uint32_t plat_ic_get_pending_interrupt_type()
  * the GIC cpu interface. INTR_ID_UNAVAILABLE is returned when there is no
  * interrupt pending.
  ******************************************************************************/
-uint32_t plat_ic_get_pending_interrupt_id()
+uint32_t plat_ic_get_pending_interrupt_id(void)
 {
 	uint32_t id, gicc_base;
 
@@ -370,7 +370,7 @@ uint32_t plat_ic_get_pending_interrupt_id()
  * This functions reads the GIC cpu interface Interrupt Acknowledge register
  * to start handling the pending interrupt. It returns the contents of the IAR.
  ******************************************************************************/
-uint32_t plat_ic_acknowledge_interrupt()
+uint32_t plat_ic_acknowledge_interrupt(void)
 {
 	return gicc_read_IAR(fvp_get_cfgvar(CONFIG_GICC_ADDR));
 }
diff --git a/plat/fvp/fvp_topology.c b/plat/fvp/fvp_topology.c
index cf21503..49f7daf 100644
--- a/plat/fvp/fvp_topology.c
+++ b/plat/fvp/fvp_topology.c
@@ -180,7 +180,7 @@ unsigned int plat_get_aff_state(unsigned int aff_lvl,
  * Handy optimization to prevent the psci implementation from traversing through
  * affinity levels which are not present while detecting the platform topology.
  ******************************************************************************/
-int plat_get_max_afflvl()
+int plat_get_max_afflvl(void)
 {
 	return MPIDR_AFFLVL1;
 }
@@ -190,7 +190,7 @@ int plat_get_max_afflvl()
  * the FVP flavour its running on. We construct all the mpidrs we can handle
  * and rely on the PWRC.PSYSR to flag absent cpus when their status is queried.
  ******************************************************************************/
-int fvp_setup_topology()
+int fvp_setup_topology(void)
 {
 	unsigned char aff0, aff1, aff_state, aff0_offset = 0;
 	unsigned long mpidr;