diff options
| author | Andrew Thoelke <andrew.thoelke@arm.com> | 2014-05-22 13:44:47 +0100 |
|---|---|---|
| committer | Andrew Thoelke <andrew.thoelke@arm.com> | 2014-05-23 08:53:03 +0100 |
| commit | 445fe84f988f61c01503a12eff591bc97dad06cd (patch) | |
| tree | 023c329040c4cbc026aa196522e839673ace7329 /plat | |
| parent | 399fb08fff2e4a0cad4cd1cf0ece84db6670447f (diff) | |
Limit BL3-1 read/write access to SRAM
At present BL3-1 has access to all of the SRAM, including
regions that are mapped as read-only and non-cacheable by other
firmware images.
This patch restricts BL3-1 to only be able to read/write from
memory used for its own data sections
Change-Id: I26cda1b9ba803d91a9eacda768f3ce7032c6db94
Conflicts:
plat/fvp/bl31_plat_setup.c
Diffstat (limited to 'plat')
| -rw-r--r-- | plat/fvp/bl31_plat_setup.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/plat/fvp/bl31_plat_setup.c b/plat/fvp/bl31_plat_setup.c index 033a8fa..7b60a78 100644 --- a/plat/fvp/bl31_plat_setup.c +++ b/plat/fvp/bl31_plat_setup.c @@ -210,8 +210,8 @@ void bl31_plat_arch_setup() fvp_cci_setup(); #endif - configure_mmu_el3(TZRAM_BASE, - TZRAM_SIZE, + configure_mmu_el3(BL31_RO_BASE, + (BL31_COHERENT_RAM_LIMIT - BL31_RO_BASE), BL31_RO_BASE, BL31_RO_LIMIT, BL31_COHERENT_RAM_BASE, |