sun50iw1p1: Adjust clock initialisation to follow Allwinner's guidance

Initialisation of clocks on Allwinner's CPUs has always been a bit tricky and
should follow the following guidance:
1. Bus clock dividers should be adjusted first to keep the bus clocks within
   their operating limits for both the new frequency _before_ changing
   the PLL (compare to section 3.3.6.2. in the A64 User's Guide v1.0).
2. PLLs should first be setup (with the enable-bit cleared), then be enabled
   and finally polled for the stable-bit to indicate the a PLL lock (compare
   how boot0 and Allwinner's linux releases have been changing PLLs for the
   A31 and subsequent chips).
3. Additionally Allwinner always injects extra delays after the PLL lock has
   triggered and after the clock source is changed.

Without these changes, the A64 will not reliably come up beyond the clock
initialisation w/ the recurrence of failure differing between individual
parts (i.e. seemingly process-dependent).

Note, that these changes and the observed failures are in line with our
experience on the A31 and A80.

X-AffectedPlatforms: A64-uQ7
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>

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