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| author | Andrew Thoelke <andrew.thoelke@arm.com> | 2014-05-23 12:14:37 +0100 |
|---|---|---|
| committer | Andrew Thoelke <andrew.thoelke@arm.com> | 2014-05-23 12:14:37 +0100 |
| commit | f53d0fce3f8e13529d823c22ce61dc0e0fdf0ffd (patch) | |
| tree | 4428e24e078c9214437734408046c3e1c2674f86 /plat/fvp | |
| parent | 8957fc76aa58cb66635b872b80e8a44be250a2ba (diff) | |
| parent | 638363eb5f548773c4eb7c9c0d21b87576064f28 (diff) | |
Merge pull request #101 from sandrine-bailleux:sb/tf-issue-81-v2
Diffstat (limited to 'plat/fvp')
| -rw-r--r-- | plat/fvp/platform.h | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/plat/fvp/platform.h b/plat/fvp/platform.h index 4c0f38f..786988c 100644 --- a/plat/fvp/platform.h +++ b/plat/fvp/platform.h @@ -245,14 +245,30 @@ #define PLAT_AFF1_ON 0x3 /******************************************************************************* + * BL1 specific defines. + * BL1 RW data is relocated from ROM to RAM at runtime so we need 2 sets of + * addresses. + ******************************************************************************/ +#define BL1_RO_BASE TZROM_BASE +#define BL1_RO_LIMIT (TZROM_BASE + TZROM_SIZE) +#define BL1_RW_BASE TZRAM_BASE +#define BL1_RW_LIMIT BL31_BASE + +/******************************************************************************* * BL2 specific defines. ******************************************************************************/ #define BL2_BASE (TZRAM_BASE + TZRAM_SIZE - 0xc000) +#define BL2_LIMIT (TZRAM_BASE + TZRAM_SIZE) /******************************************************************************* * BL31 specific defines. ******************************************************************************/ #define BL31_BASE (TZRAM_BASE + 0x6000) +#if TSP_RAM_LOCATION_ID == TSP_IN_TZRAM +#define BL31_LIMIT BL32_BASE +#elif TSP_RAM_LOCATION_ID == TSP_IN_TZDRAM +#define BL31_LIMIT BL2_BASE +#endif /******************************************************************************* * BL32 specific defines. |