diff options
| author | Achin Gupta <achin.gupta@arm.com> | 2014-05-09 12:00:17 +0100 |
|---|---|---|
| committer | Achin Gupta <achin.gupta@arm.com> | 2014-05-22 17:47:20 +0100 |
| commit | fa9c08b7d117cb736911288668f9fd987505b4e3 (patch) | |
| tree | c935c5a3ab474265b51c2b1c8c53ec798e9fee2c /lib/aarch64 | |
| parent | dce74b891e0e6020d0a18384e32f280133631d9b (diff) | |
Use secure timer to generate S-EL1 interrupts
This patch adds support in the TSP to program the secure physical
generic timer to generate a EL-1 interrupt every half second. It also
adds support for maintaining the timer state across power management
operations. The TSPD ensures that S-EL1 can access the timer by
programming the SCR_EL3.ST bit.
This patch does not actually enable the timer. This will be done in a
subsequent patch once the complete framework for handling S-EL1
interrupts is in place.
Change-Id: I1b3985cfb50262f60824be3a51c6314ce90571bc
Diffstat (limited to 'lib/aarch64')
| -rw-r--r-- | lib/aarch64/sysreg_helpers.S | 37 |
1 files changed, 37 insertions, 0 deletions
diff --git a/lib/aarch64/sysreg_helpers.S b/lib/aarch64/sysreg_helpers.S index c86fdba..925e93e 100644 --- a/lib/aarch64/sysreg_helpers.S +++ b/lib/aarch64/sysreg_helpers.S @@ -142,6 +142,15 @@ .globl read_cntfrq_el0 .globl write_cntfrq_el0 + .globl read_cntps_ctl_el1 + .globl write_cntps_ctl_el1 + + .globl read_cntps_cval_el1 + .globl write_cntps_cval_el1 + + .globl read_cntps_tval_el1 + .globl write_cntps_tval_el1 + .globl read_scr .globl write_scr @@ -151,6 +160,7 @@ .globl read_midr .globl read_mpidr + .globl read_cntpct_el0 .globl read_current_el .globl read_id_pfr1_el1 .globl read_id_aa64pfr0_el1 @@ -672,6 +682,33 @@ func write_cntfrq_el0 msr cntfrq_el0, x0 ret +func read_cntps_ctl_el1 + mrs x0, cntps_ctl_el1 + ret + +func write_cntps_ctl_el1 + msr cntps_ctl_el1, x0 + ret + +func read_cntps_cval_el1 + mrs x0, cntps_cval_el1 + ret + +func write_cntps_cval_el1 + msr cntps_cval_el1, x0 + ret + +func read_cntps_tval_el1 + mrs x0, cntps_tval_el1 + ret + +func write_cntps_tval_el1 + msr cntps_tval_el1, x0 + ret + +func read_cntpct_el0 + mrs x0, cntpct_el0 + ret func read_cpuectlr mrs x0, CPUECTLR_EL1 |