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authordanh-arm <dan.handley@arm.com>2014-07-28 14:28:40 +0100
committerdanh-arm <dan.handley@arm.com>2014-07-28 14:28:40 +0100
commit6397bf6a99d785caa9b50016cd6c8eb76083c117 (patch)
tree5e9ffd003cb8046b7eba285907bdedf4bd8c20ba /lib/aarch64
parent9fd412770f1a7d9c68731a21f157a326db3c5725 (diff)
parent8c106902368c40e14c558a0ab91cc57defdc7e81 (diff)
Merge pull request #172 from soby-mathew/sm/asm_assert
Introduce asm assert and optimize crash reporting
Diffstat (limited to 'lib/aarch64')
-rw-r--r--lib/aarch64/misc_helpers.S12
1 files changed, 10 insertions, 2 deletions
diff --git a/lib/aarch64/misc_helpers.S b/lib/aarch64/misc_helpers.S
index 439ca28..f605bf4 100644
--- a/lib/aarch64/misc_helpers.S
+++ b/lib/aarch64/misc_helpers.S
@@ -30,6 +30,7 @@
#include <arch.h>
#include <asm_macros.S>
+#include <assert_macros.S>
.globl get_afflvl_shift
.globl mpidr_mask_lower_afflvls
@@ -46,7 +47,6 @@
.globl enable_vfp
#endif
-
func get_afflvl_shift
cmp x0, #3
cinc x0, x0, eq
@@ -79,6 +79,10 @@ func smc
* -----------------------------------------------------------------------
*/
func zeromem16
+#if ASM_ASSERTION
+ tst x0, #0xf
+ ASM_ASSERT(eq)
+#endif
add x2, x0, x1
/* zero 16 bytes at a time */
z_loop16:
@@ -105,6 +109,11 @@ z_end: ret
* --------------------------------------------------------------------------
*/
func memcpy16
+#if ASM_ASSERTION
+ orr x3, x0, x1
+ tst x3, #0xf
+ ASM_ASSERT(eq)
+#endif
/* copy 16 bytes at a time */
m_loop16:
cmp x2, #16
@@ -145,7 +154,6 @@ func disable_mmu_icache_el3
mov x1, #(SCTLR_M_BIT | SCTLR_C_BIT | SCTLR_I_BIT)
b do_disable_mmu
-
/* ---------------------------------------------------------------------------
* Enable the use of VFP at EL3
* ---------------------------------------------------------------------------