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| author | Andrew Thoelke <andrew.thoelke@arm.com> | 2014-04-28 12:06:18 +0100 |
|---|---|---|
| committer | Andrew Thoelke <andrew.thoelke@arm.com> | 2014-05-07 11:23:50 +0100 |
| commit | 2f5dcfef1db42f3b073ae657f8a94925abecd768 (patch) | |
| tree | 378833fa34bed975066532e5b01cd85390cdc144 /lib/aarch64 | |
| parent | 8cec598ba3b689b86d9dfc58bca5610bdc48f55a (diff) | |
Replace disable_mmu with assembler version
disable_mmu() cannot work as a C function as there is no control
over data accesses generated by the compiler between disabling and
cleaning the data cache. This results in reading stale data from
main memory.
As assembler version is provided for EL3, and a variant that also
disables the instruction cache which is now used by the BL1
exception handling function.
Fixes ARM-software/tf-issues#147
Change-Id: I0cf394d2579a125a23c2f2989c2e92ace6ddb1a6
Diffstat (limited to 'lib/aarch64')
| -rw-r--r-- | lib/aarch64/misc_helpers.S | 27 |
1 files changed, 27 insertions, 0 deletions
diff --git a/lib/aarch64/misc_helpers.S b/lib/aarch64/misc_helpers.S index c33ade2..bccc936 100644 --- a/lib/aarch64/misc_helpers.S +++ b/lib/aarch64/misc_helpers.S @@ -79,6 +79,9 @@ .globl zeromem16 .globl memcpy16 + .globl disable_mmu_el3 + .globl disable_mmu_icache_el3 + func get_afflvl_shift cmp x0, #3 @@ -332,3 +335,27 @@ m_loop1: subs x2, x2, #1 b.ne m_loop1 m_end: ret + +/* --------------------------------------------------------------------------- + * Disable the MMU at EL3 + * This is implemented in assembler to ensure that the data cache is cleaned + * and invalidated after the MMU is disabled without any intervening cacheable + * data accesses + * --------------------------------------------------------------------------- + */ + +func disable_mmu_el3 + mov x1, #(SCTLR_M_BIT | SCTLR_C_BIT) +do_disable_mmu: + mrs x0, sctlr_el3 + bic x0, x0, x1 + msr sctlr_el3, x0 + isb // ensure MMU is off + mov x0, #DCCISW // DCache clean and invalidate + b dcsw_op_all + + +func disable_mmu_icache_el3 + mov x1, #(SCTLR_M_BIT | SCTLR_C_BIT | SCTLR_I_BIT) + b do_disable_mmu + |