diff options
| author | Achin Gupta <achin.gupta@arm.com> | 2014-07-18 18:38:28 +0100 |
|---|---|---|
| committer | Achin Gupta <achin.gupta@arm.com> | 2014-07-28 10:10:22 +0100 |
| commit | ec3c10039bdc2c1468a8ba95fbbe9de78628eea5 (patch) | |
| tree | b8781fc14291cb3afd32a49ef8bbe5f60bdf0188 /include | |
| parent | 539a7b383d52493a94df4f5da8f74aa102429fa0 (diff) | |
Simplify management of SCTLR_EL3 and SCTLR_EL1
This patch reworks the manner in which the M,A, C, SA, I, WXN & EE bits of
SCTLR_EL3 & SCTLR_EL1 are managed. The EE bit is cleared immediately after reset
in EL3. The I, A and SA bits are set next in EL3 and immediately upon entry in
S-EL1. These bits are no longer managed in the blX_arch_setup() functions. They
do not have to be saved and restored either. The M, WXN and optionally the C
bit are set in the enable_mmu_elX() function. This is done during both the warm
and cold boot paths.
Fixes ARM-software/tf-issues#226
Change-Id: Ie894d1a07b8697c116960d858cd138c50bc7a069
Diffstat (limited to 'include')
| -rw-r--r-- | include/lib/aarch64/arch.h | 3 |
1 files changed, 0 insertions, 3 deletions
diff --git a/include/lib/aarch64/arch.h b/include/lib/aarch64/arch.h index ff91efc..0427208 100644 --- a/include/lib/aarch64/arch.h +++ b/include/lib/aarch64/arch.h @@ -129,11 +129,8 @@ #define SCTLR_A_BIT (1 << 1) #define SCTLR_C_BIT (1 << 2) #define SCTLR_SA_BIT (1 << 3) -#define SCTLR_B_BIT (1 << 7) -#define SCTLR_Z_BIT (1 << 11) #define SCTLR_I_BIT (1 << 12) #define SCTLR_WXN_BIT (1 << 19) -#define SCTLR_EXCEPTION_BITS (0x3 << 6) #define SCTLR_EE_BIT (1 << 25) /* CPUECTLR definitions */ |