diff options
| author | Andre Przywara <andre.przywara@arm.com> | 2016-02-03 23:44:36 +0000 |
|---|---|---|
| committer | Andre Przywara <andre.przywara@arm.com> | 2016-02-04 09:00:42 +0000 |
| commit | 90fc243e9256775c85f8763e8fa1b2b59e67d0ce (patch) | |
| tree | 4293050433bd6237830ec824e8334a90bf400af4 /drivers/arm/gic/arm_gic.c | |
| parent | 14b6608c9a2eba27ef36cc3e0806c9fa6d5555b0 (diff) | |
Merge in files from Allwinners lichee BSP tarball
The Pine64 Wiki[1] links to a BSP tarball, among other things
containing a dump of an ARM Trusted Firmware source tree with
Allwinner changes on top.
Since the tarball does not contain any version history information
about the changes, this commit is just the diff between the ATF 1.0
release and the files from the Allwinner provided tarball.
The executable flag from many source has been removed.
[1] http://wiki.pine64.org/index.php/Pine_A64_Software_Release#Linux_BSP_Related
Diffstat (limited to 'drivers/arm/gic/arm_gic.c')
| -rw-r--r-- | drivers/arm/gic/arm_gic.c | 20 |
1 files changed, 18 insertions, 2 deletions
diff --git a/drivers/arm/gic/arm_gic.c b/drivers/arm/gic/arm_gic.c index 86aaa9a..0600af8 100644 --- a/drivers/arm/gic/arm_gic.c +++ b/drivers/arm/gic/arm_gic.c @@ -47,6 +47,9 @@ static unsigned long g_gicr_base; static const unsigned int *g_irq_sec_ptr; static unsigned int g_num_irqs; +void gic_sunxi_distributor_init(void); +void gic_sunxi_cpuif_init(void); + /******************************************************************************* * This function does some minimal GICv3 configuration. The Firmware itself does @@ -161,6 +164,7 @@ static void gicv3_cpuif_deactivate(void) ******************************************************************************/ void arm_gic_cpuif_setup(void) { + unsigned int val; assert(g_gicc_base); @@ -174,11 +178,13 @@ void arm_gic_cpuif_setup(void) if (((val >> GICC_IIDR_ARCH_SHIFT) & GICC_IIDR_ARCH_MASK) >= 3) gicv3_cpuif_setup(); + val = ENABLE_GRP0 | FIQ_EN | FIQ_BYP_DIS_GRP0; val |= IRQ_BYP_DIS_GRP0 | FIQ_BYP_DIS_GRP1 | IRQ_BYP_DIS_GRP1; gicc_write_pmr(g_gicc_base, GIC_PRI_MASK); gicc_write_ctlr(g_gicc_base, val); + } /******************************************************************************* @@ -238,6 +244,7 @@ void arm_gic_pcpu_distif_setup(void) ******************************************************************************/ static void arm_gic_distif_setup(void) { + unsigned int num_ints, ctlr, index, irq_num; /* Disable the distributor before going further */ @@ -273,6 +280,7 @@ static void arm_gic_distif_setup(void) arm_gic_pcpu_distif_setup(); gicd_write_ctlr(g_gicd_base, ctlr | ENABLE_GRP0); + } /******************************************************************************* @@ -301,8 +309,16 @@ void arm_gic_init(unsigned int gicc_base, ******************************************************************************/ void arm_gic_setup(void) { - arm_gic_cpuif_setup(); - arm_gic_distif_setup(); + if(0) + { + arm_gic_cpuif_setup(); + arm_gic_distif_setup(); + }else + { + gic_sunxi_cpuif_init(); + gic_sunxi_distributor_init(); + } + } /******************************************************************************* |