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| author | Soby Mathew <soby.mathew@arm.com> | 2014-05-09 20:49:17 +0100 |
|---|---|---|
| committer | Andrew Thoelke <andrew.thoelke@arm.com> | 2014-05-23 08:46:21 +0100 |
| commit | 239b04fa31647100c537852b4a3fc8bd47e33aa6 (patch) | |
| tree | 3b2c73b2d39ed0a460375b42f1f3143703646fbc /bl32/tsp/tsp_interrupt.c | |
| parent | a20a81e5b4a19969673f672523b946647f5d545d (diff) | |
Non-Secure Interrupt support during Standard SMC processing in TSP
Implements support for Non Secure Interrupts preempting the
Standard SMC call in EL1. Whenever an IRQ is trapped in the
Secure world we securely handover to the Normal world
to process the interrupt. The normal world then issues
"resume" smc call to resume the previous interrupted SMC call.
Fixes ARM-software/tf-issues#105
Change-Id: I72b760617dee27438754cdfc9fe9bcf4cc024858
Diffstat (limited to 'bl32/tsp/tsp_interrupt.c')
| -rw-r--r-- | bl32/tsp/tsp_interrupt.c | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/bl32/tsp/tsp_interrupt.c b/bl32/tsp/tsp_interrupt.c index d5d02c3..5719c06 100644 --- a/bl32/tsp/tsp_interrupt.c +++ b/bl32/tsp/tsp_interrupt.c @@ -107,3 +107,18 @@ int32_t tsp_fiq_handler() return 0; } + +int32_t tsp_irq_received() +{ + uint64_t mpidr = read_mpidr(); + uint32_t linear_id = platform_get_core_pos(mpidr); + + tsp_stats[linear_id].irq_count++; + spin_lock(&console_lock); + printf("TSP: cpu 0x%x received irq\n\r", mpidr); + INFO("cpu 0x%x: %d irq requests \n", + mpidr, tsp_stats[linear_id].irq_count); + spin_unlock(&console_lock); + + return TSP_PREEMPTED; +} |