diff options
| author | Achin Gupta <achin.gupta@arm.com> | 2014-06-26 09:58:52 +0100 |
|---|---|---|
| committer | Achin Gupta <achin.gupta@arm.com> | 2014-07-19 23:31:53 +0100 |
| commit | b51da821821cfda0d44f09a6f92fdc5933f9b23b (patch) | |
| tree | 01d72a57badfa7cc19c5530d64f4c308b6d37799 /bl32/tsp/aarch64 | |
| parent | afff8cbdd816ca9b0d71ab54882ce70b21ed84e1 (diff) | |
Remove coherent stack usage from the warm boot path
This patch uses stacks allocated in normal memory to enable the MMU early in the
warm boot path thus removing the dependency on stacks allocated in coherent
memory. Necessary cache and stack maintenance is performed when a cpu is being
powered down and up. This avoids any coherency issues that can arise from
reading speculatively fetched stale stack memory from another CPUs cache. These
changes affect the warm boot path in both BL3-1 and BL3-2.
The EL3 system registers responsible for preserving the MMU state are not saved
and restored any longer. Static values are used to program these system
registers when a cpu is powered on or resumed from suspend.
Change-Id: I8357e2eb5eb6c5f448492c5094b82b8927603784
Diffstat (limited to 'bl32/tsp/aarch64')
| -rw-r--r-- | bl32/tsp/aarch64/tsp_entrypoint.S | 43 |
1 files changed, 33 insertions, 10 deletions
diff --git a/bl32/tsp/aarch64/tsp_entrypoint.S b/bl32/tsp/aarch64/tsp_entrypoint.S index c5ec9e3..7a1797e 100644 --- a/bl32/tsp/aarch64/tsp_entrypoint.S +++ b/bl32/tsp/aarch64/tsp_entrypoint.S @@ -31,6 +31,7 @@ #include <arch.h> #include <asm_macros.S> #include <tsp.h> +#include <xlat_tables.h> .globl tsp_entrypoint @@ -204,26 +205,48 @@ func tsp_cpu_on_entry isb /* -------------------------------------------- - * Give ourselves a small coherent stack to - * ease the pain of initializing the MMU + * Give ourselves a stack whose memory will be + * marked as Normal-IS-WBWA when the MMU is + * enabled. * -------------------------------------------- */ mrs x0, mpidr_el1 - bl platform_set_coherent_stack + bl platform_set_stack - /* --------------------------------------------- - * Initialise the MMU - * --------------------------------------------- + /* -------------------------------------------- + * Enable the MMU with the DCache disabled. It + * is safe to use stacks allocated in normal + * memory as a result. All memory accesses are + * marked nGnRnE when the MMU is disabled. So + * all the stack writes will make it to memory. + * All memory accesses are marked Non-cacheable + * when the MMU is enabled but D$ is disabled. + * So used stack memory is guaranteed to be + * visible immediately after the MMU is enabled + * Enabling the DCache at the same time as the + * MMU can lead to speculatively fetched and + * possibly stale stack memory being read from + * other caches. This can lead to coherency + * issues. + * -------------------------------------------- */ + mov x0, #DISABLE_DCACHE bl bl32_plat_enable_mmu /* --------------------------------------------- - * Give ourselves a stack allocated in Normal - * -IS-WBWA memory + * Enable the Data cache now that the MMU has + * been enabled. The stack has been unwound. It + * will be written first before being read. This + * will invalidate any stale cache lines resi- + * -dent in other caches. We assume that + * interconnect coherency has been enabled for + * this cluster by EL3 firmware. * --------------------------------------------- */ - mrs x0, mpidr_el1 - bl platform_set_stack + mrs x0, sctlr_el1 + orr x0, x0, #SCTLR_C_BIT + msr sctlr_el1, x0 + isb /* --------------------------------------------- * Enter C runtime to perform any remaining |