diff options
| author | Jeenu Viswambharan <jeenu.viswambharan@arm.com> | 2014-05-12 15:28:47 +0100 |
|---|---|---|
| committer | Jeenu Viswambharan <jeenu.viswambharan@arm.com> | 2014-05-16 17:11:31 +0100 |
| commit | 2da8d8bfc0877b9c723514133554dfee4c0638f1 (patch) | |
| tree | 5178aafe28b80e33b6581663bee66b9d2194688a /bl31 | |
| parent | c3c1e9b0abe1a879dad4400421ad00849231eb3c (diff) | |
Add build configuration for timer save/restore
At present, non-secure timer register contents are saved and restored as
part of world switch by BL3-1. This effectively means that the
non-secure timer stops, and non-secure timer interrupts are prevented
from asserting until BL3-1 switches back, introducing latency for
non-secure services. Often, secure world might depend on alternate
sources for secure interrupts (secure timer or platform timer) instead
of non-secure timers, in which case this save and restore is
unnecessary.
This patch introduces a boolean build-time configuration NS_TIMER_SWITCH
to choose whether or not to save and restore non-secure timer registers
upon world switch. The default choice is made not to save and restore
them.
Fixes ARM-software/tf-issues#148
Change-Id: I1b9d623606acb9797c3e0b02fb5ec7c0a414f37e
Diffstat (limited to 'bl31')
| -rw-r--r-- | bl31/aarch64/context.S | 14 |
1 files changed, 12 insertions, 2 deletions
diff --git a/bl31/aarch64/context.S b/bl31/aarch64/context.S index 45d4a22..d0bca64 100644 --- a/bl31/aarch64/context.S +++ b/bl31/aarch64/context.S @@ -172,6 +172,8 @@ func el1_sysregs_context_save mrs x9, vbar_el1 stp x17, x9, [x0, #CTX_CONTEXTIDR_EL1] + /* Save NS timer registers if the build has instructed so */ +#if NS_TIMER_SWITCH mrs x10, cntp_ctl_el0 mrs x11, cntp_cval_el0 stp x10, x11, [x0, #CTX_CNTP_CTL_EL0] @@ -181,8 +183,11 @@ func el1_sysregs_context_save stp x12, x13, [x0, #CTX_CNTV_CTL_EL0] mrs x14, cntkctl_el1 + str x14, [x0, #CTX_CNTKCTL_EL1] +#endif + mrs x15, fpexc32_el2 - stp x14, x15, [x0, #CTX_CNTKCTL_EL1] + str x15, [x0, #CTX_FP_FPEXC32_EL2] ret @@ -253,6 +258,8 @@ func el1_sysregs_context_restore msr contextidr_el1, x17 msr vbar_el1, x9 + /* Restore NS timer registers if the build has instructed so */ +#if NS_TIMER_SWITCH ldp x10, x11, [x0, #CTX_CNTP_CTL_EL0] msr cntp_ctl_el0, x10 msr cntp_cval_el0, x11 @@ -261,8 +268,11 @@ func el1_sysregs_context_restore msr cntv_ctl_el0, x12 msr cntv_cval_el0, x13 - ldp x14, x15, [x0, #CTX_CNTKCTL_EL1] + ldr x14, [x0, #CTX_CNTKCTL_EL1] msr cntkctl_el1, x14 +#endif + + ldr x15, [x0, #CTX_FP_FPEXC32_EL2] msr fpexc32_el2, x15 /* No explict ISB required here as ERET covers it */ |