sun50iw1p1: Adjust PMIC setting for the A64-uQ7 (DDR3L and GbE PHY)

For the A64-uQ7 we should set up DCDC5 (DDR) to 1.36V and DCDC4 to 1.2V
(for the Micrel GbE PHY).  Note that a higher DCDC5 setting (i.e. 1.5V)
will also work safely, but we expect a power-saving under high system load
from using the lower DDR3L voltage supported by our RAM.

Per my discussion with Andre, board-specific power initialisation should
eventually be conditionalised on the FDT, as seen by the ATF.  However,
this will require the ATF to be rebased to a more current ATF source
bae first.

X-AffectedPlatforms: A64-uQ7
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>

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