diff options
| author | Harry Liebel <Harry.Liebel@arm.com> | 2014-01-14 18:11:48 +0000 |
|---|---|---|
| committer | Dan Handley <dan.handley@arm.com> | 2014-01-17 10:27:53 +0000 |
| commit | 4f6036834fb7f53e3002c37af1c9d0681e8ef675 (patch) | |
| tree | af1bdd052679342b63b7b7a0d44cb51d34dc1e19 /bl1 | |
| parent | e83b0cadc67882c1ba7f430d16dab80c9b3a0228 (diff) | |
Do not trap access to floating point registers
Traps when accessing architectural features are disabled by clearing bits
in CPTR_EL3 during early boot, including accesses to floating point
registers. The value of this register was previously undetermined, causing
unwanted traps to EL3. Future EL3 code (for example, context save/restore
code) may use floating point registers, although they are not used by current
code.
Also, the '-mgeneral-regs-only' flag is enabled in the GCC settings to
prevent generation of code that uses floating point registers.
Change-Id: I9a03675f6387bbbee81a6f2c9ccf81150db03747
Diffstat (limited to 'bl1')
| -rw-r--r-- | bl1/aarch64/bl1_arch_setup.c | 3 | ||||
| -rw-r--r-- | bl1/aarch64/bl1_entrypoint.S | 23 |
2 files changed, 23 insertions, 3 deletions
diff --git a/bl1/aarch64/bl1_arch_setup.c b/bl1/aarch64/bl1_arch_setup.c index f308715..3a528e1 100644 --- a/bl1/aarch64/bl1_arch_setup.c +++ b/bl1/aarch64/bl1_arch_setup.c @@ -61,9 +61,6 @@ void bl1_arch_setup(void) enable_serror(); enable_debug_exceptions(); - /* Do not trap coprocessor accesses from lower ELs to EL3 */ - write_cptr_el3(0); - /* Read the frequency from Frequency modes table */ counter_base_frequency = mmio_read_32(SYS_CNTCTL_BASE + CNTFID_OFF); /* The first entry of the frequency modes table must not be 0 */ diff --git a/bl1/aarch64/bl1_entrypoint.S b/bl1/aarch64/bl1_entrypoint.S index 9bb9c34..f5e4420 100644 --- a/bl1/aarch64/bl1_entrypoint.S +++ b/bl1/aarch64/bl1_entrypoint.S @@ -57,6 +57,29 @@ reset_handler:; .type reset_handler, %function adr x0, early_exceptions msr vbar_el3, x0 + /* --------------------------------------------------------------------- + * The initial state of the Architectural feature trap register + * (CPTR_EL3) is unknown and it must be set to a known state. All + * feature traps are disabled. Some bits in this register are marked as + * Reserved and should not be modified. + * + * CPTR_EL3.TCPAC: This causes a direct access to the CPACR_EL1 from EL1 + * or the CPTR_EL2 from EL2 to trap to EL3 unless it is trapped at EL2. + * CPTR_EL3.TTA: This causes access to the Trace functionality to trap + * to EL3 when executed from EL0, EL1, EL2, or EL3. If system register + * access to trace functionality is not supported, this bit is RES0. + * CPTR_EL3.TFP: This causes instructions that access the registers + * associated with Floating Point and Advanced SIMD execution to trap + * to EL3 when executed from any exception level, unless trapped to EL1 + * or EL2. + * --------------------------------------------------------------------- + */ + mrs x0, cptr_el3 + bic w0, w0, #TCPAC_BIT + bic w0, w0, #TTA_BIT + bic w0, w0, #TFP_BIT + msr cptr_el3, x0 + /* --------------------------------------------- * Enable the instruction cache. * --------------------------------------------- |