diff options
| author | Andrew Thoelke <andrew.thoelke@arm.com> | 2014-04-28 12:06:18 +0100 |
|---|---|---|
| committer | Andrew Thoelke <andrew.thoelke@arm.com> | 2014-05-07 11:23:50 +0100 |
| commit | 2f5dcfef1db42f3b073ae657f8a94925abecd768 (patch) | |
| tree | 378833fa34bed975066532e5b01cd85390cdc144 /bl1 | |
| parent | 8cec598ba3b689b86d9dfc58bca5610bdc48f55a (diff) | |
Replace disable_mmu with assembler version
disable_mmu() cannot work as a C function as there is no control
over data accesses generated by the compiler between disabling and
cleaning the data cache. This results in reading stale data from
main memory.
As assembler version is provided for EL3, and a variant that also
disables the instruction cache which is now used by the BL1
exception handling function.
Fixes ARM-software/tf-issues#147
Change-Id: I0cf394d2579a125a23c2f2989c2e92ace6ddb1a6
Diffstat (limited to 'bl1')
| -rw-r--r-- | bl1/aarch64/bl1_exceptions.S | 12 |
1 files changed, 2 insertions, 10 deletions
diff --git a/bl1/aarch64/bl1_exceptions.S b/bl1/aarch64/bl1_exceptions.S index 7f930d8..71fd4cd 100644 --- a/bl1/aarch64/bl1_exceptions.S +++ b/bl1/aarch64/bl1_exceptions.S @@ -212,18 +212,10 @@ func process_exception /* --------------------------------------------- * If BL31 is to be executed in EL3 as well * then turn off the MMU so that it can perform - * its own setup. TODO: Assuming flat mapped - * translations here. Also all should go into a - * separate MMU teardown function + * its own setup. * --------------------------------------------- */ - mov x1, #(SCTLR_M_BIT | SCTLR_C_BIT | SCTLR_I_BIT) - bl read_sctlr_el3 - bic x0, x0, x1 - bl write_sctlr_el3 - isb - mov x0, #DCCISW - bl dcsw_op_all + bl disable_mmu_icache_el3 bl tlbialle3 skip_mmu_teardown: ldp x6, x7, [sp, #0x30] |