diff options
| author | Jeenu Viswambharan <jeenu.viswambharan@arm.com> | 2014-01-07 10:21:18 +0000 |
|---|---|---|
| committer | Dan Handley <dan.handley@arm.com> | 2014-03-10 14:17:59 +0000 |
| commit | 1c297bf015226c182b66498d5a64b8b51c7624f5 (patch) | |
| tree | 599f1d5a6bec18bc5ce9f9964c0c4a0b6f0955eb /bl1 | |
| parent | 92a12866e6ab01c284f7aff01818c65851880bfd (diff) | |
Move architecture timer setup to platform-specific code
At present, bl1_arch_setup() and bl31_arch_setup() program the counter
frequency using a value from the memory mapped generic timer. The
generic timer however is not necessarily present on all ARM systems
(although it is architected to be present on all server systems).
This patch moves the timer setup to platform-specific code and updates
the relevant documentation. Also, CNTR.FCREQ is set as the specification
requires the bit corresponding to the counter's frequency to be set when
enabling. Since we intend to use the base frequency, set bit 8.
Fixes ARM-software/tf-issues#24
Change-Id: I32c52cf882253e01f49056f47c58c23e6f422652
Diffstat (limited to 'bl1')
| -rw-r--r-- | bl1/aarch64/bl1_arch_setup.c | 8 |
1 files changed, 0 insertions, 8 deletions
diff --git a/bl1/aarch64/bl1_arch_setup.c b/bl1/aarch64/bl1_arch_setup.c index 3a528e1..e82ad09 100644 --- a/bl1/aarch64/bl1_arch_setup.c +++ b/bl1/aarch64/bl1_arch_setup.c @@ -39,7 +39,6 @@ void bl1_arch_setup(void) { unsigned long tmp_reg = 0; - unsigned int counter_base_frequency; /* Enable alignment checks and set the exception endianess to LE */ tmp_reg = read_sctlr(); @@ -61,13 +60,6 @@ void bl1_arch_setup(void) enable_serror(); enable_debug_exceptions(); - /* Read the frequency from Frequency modes table */ - counter_base_frequency = mmio_read_32(SYS_CNTCTL_BASE + CNTFID_OFF); - /* The first entry of the frequency modes table must not be 0 */ - assert(counter_base_frequency != 0); - - /* Program the counter frequency */ - write_cntfrq_el0(counter_base_frequency); return; } |